Chip Scale Package (CSP) solder joint reliability and modeling

Microelectronics Reliability

Volumn 39, Issue 4, 1999, Pages 463-477

  Amagai, M ^a  

^a Texas Instruments Japan Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CORRELATION METHODS; CREEP; ELECTRONICS PACKAGING; EXTRAPOLATION; FINITE ELEMENT METHOD; PRINTED CIRCUIT DESIGN; SEMICONDUCTOR DEVICE MODELS; SOLDERED JOINTS; STRAIN RATE; SURFACE MOUNT TECHNOLOGY; VISCOPLASTICITY; WEIBULL DISTRIBUTION;

CHIP SCALE PACKAGE (CSP) SOLDER JOINTS; VISCOPLASTIC FLOW EQUATIONS;

ULSI CIRCUITS;

EID: 0032632103     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(99)00017-7     Document Type: Article

References (10)

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