Fully parallel on-chip learning hardware neural network for real-time control

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 1999, Pages

  Liu, Jin ^a   Brooke, Martin ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SUB-OPTIMAL CONTROL; PARALLEL ON-CHIP LEARNING HARDWARE NEURAL NETWORKS; REAL-TIME OUTPUT FEEDBACK CONTROL;

ADAPTIVE CONTROL SYSTEMS; COMPUTER SIMULATION; CONTROL SYSTEM ANALYSIS; CONTROL SYSTEM SYNTHESIS; FEEDBACK CONTROL; LEARNING SYSTEMS; LOGIC CIRCUITS; NONLINEAR NETWORK ANALYSIS; NONLINEAR NETWORK SYNTHESIS; OPTIMAL CONTROL SYSTEMS; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS;

NEURAL NETWORKS;

EID: 0032630854     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

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