Automatic topology optimization for analog module generators

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 961-962

  Wolf, M ^a   Kleine, U ^a  

^a OTTO VON GUERICKE UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG MODULES; MODULE GENERATOR; SOURCE CODES;

TOPOLOGY;

EID: 84893749867     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655989     Document Type: Conference Paper

References (6)

1. J. Rijmenants, et al., "ILAC: An Automated Layout Tool for Analog CMOS Circuits," IEEE J. Solid-State Circuits, Vol. 24, No. 2, pp. 417-425, April 1989.
2. H. Y. Koh, et al., "OPASYN: A Compiler for CMOS Operational Amplifiers," IEEE Trans. Computer-Aided Design, Vol. 9, No. 2, pp. 113-125, Feb. 1990.
3. V. Meyer zu Bexten, et al., "ALSYN: Flexible Rule-Based Layout Synthesis for Analog IC's," IEEE J. Solid-State Circuits, Vol. 28, No. 3, pp. 261-268, March 1993.
4. B. R. Owen, et al., "BALLISTIC: An Analog Layout Language," IEEE Custom Integrated Circuits Conference, pp. 3.5.1-3.5.4, 1995.
5. M. Wolf, et al., "A Novel Analog Module Generator Environment," Proc. The European Design &Test Conference, pp. 388-392, March 1996.
6. M. Wolf, et al., "Application Independent Module Generation in Analog Layouts," Proc. The European Design &Test Conference, p. 624, March 1997.