FPGA implementation for 2D discrete wavelet transform

Electronics Letters

Volumn 34, Issue 7, 1998, Pages 639-640

  Hung, King Chu ^a   Huang, Yu Jung ^a   Truong, Trieu Kien ^a   Wang, Chia Ming ^a  

^a I SHOU UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CORRELATION METHODS; LOGIC GATES; MATHEMATICAL OPERATORS; WAVELET TRANSFORMS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

LOGIC DESIGN;

EID: 0032473667     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19980536     Document Type: Article

References (8)

1. MALLAT, S.G.: 'A theory for multiresolution signal decomposition: The wavelet representation', IEEE Trans. Pat. Anal Mach. Intell 1989, 11, (7), pp. 674-693
2. GRZESZCZAK, A., MANDAL, M.K., PANCHANATHAN, S., and YEAP.T.: 'VLSI implementation of discrete wavelet transform', IEEE Trans. VLSI Syst., 1996, 4, (4), pp. 421-433
3. KNOWLES, G.: 'VLSI architecture for the discrete wavelet transform', Electron. Lett.. 1990, 26, (15), pp. 1184-1185
4. LEWIS, A.S., and KNOWLES. G.: 'VLSI architecture for 2D Daubechies wavelet transform without multipliers', Electron. Lett., 1991, 27, (2), pp. 171-173
5. PARHI, K., and NISHITANI, T.: 'VLSI architecture for discrete wavelet transforms', IEEE Trans. VLSI Syst., 1993, 1, (2), pp. 191-202
6. VISHWANATH, M., MICHAEL, R.M., and IRWIN, M.J.: 'VLSI architecture for the discrete wavelet transform', IEEE Trans. Circuits Syst-II Anal. Dig. Signal Process., 1995, 42, (5), pp. 305-316
7. TRUONG, T.K., HUNG. K.C., HUANG. Y.J., and TSENG. Y.S.: 'A new VLSI architecture for the 2D discrete wavelet transform'. IEEE Pacific Rim Conf. on Communications, Computers and Signal Processing, 1997, pp. 481-484
8. HUANG. Y.J., HUNG. K.C., TRUONG. T.K., and WANG. CM.: 'An FPGA prototype for the 2D discrete wavelet transform'. 1997 Multimedia Technology and Applications Symp., 1997, pp. 185-191