Influence of silicon surface integrity on device yield

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 3510, Issue , 1998, Pages 169-177

  Kimura, Yasuhiro ^a   Naruoka, Hideki ^a   Kume, Morihiko ^a   Katayama, Toshiharu ^a   Yamamoto, Hidekazu ^a   Mashiko, Yoji ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

Cu; Cu decoration; GOI; MWF; Pit; Pure water; SC 1 cleaning; SSI; Wafer surface

Indexed keywords

CLEANING; CONTAMINATION; COPPER; FAILURE ANALYSIS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; OXIDES; SCANNING ELECTRON MICROSCOPY; SILICON WAFERS; SURFACES; WATER;

COPPER DECORATION; GATE OXIDE INTEGRITY; METAL INDUCED WAFER SHAPING PROCESS FAILURE; OPTICAL SHALLOW DEFECT ANALYZER; PIT; PURE WATER; SILICON SURFACE INTEGRITY; WAFER SURFACE;

LSI CIRCUITS;

EID: 0032404570     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.324374     Document Type: Conference Paper

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