Stereo multi-bit ΣΔ D/A with asynchronous master-clock interface

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 226-227

  Kwan, Tom ^a   Adams, Robert ^a   Libert, Robert ^a  

^a ANALOG DEVICES INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CLOCKS; CMOS INTEGRATED CIRCUITS; ERRORS; FAST FOURIER TRANSFORMS; MODULATORS; PHASE LOCKED LOOPS; SIGNAL FILTERING AND PREDICTION; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE; SWITCHED FILTERS; TIMING CIRCUITS;

ASYNCHRONOUS MASTER CLOCK INTERFACE; DIGITAL PHASE LOCKED LOOP; SWITCHED CAPACITOR FILTER;

DIGITAL TO ANALOG CONVERSION;

EID: 0030083841     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)