Asynchronous logic in bit-serial arithmetic

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 1998, Pages 175-178

  Povazanec, J ^a   Choy, C S ^a   Chan, C F ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS LOGICS; BIT-SERIAL ARITHMETIC; MODIFIED HANDSHAKE PROTOCOLS; ASYNCHRONOUS LOGIC; BIT-SERIAL; COST EFFECTIVE; HANDSHAKE PROTOCOL; LOCAL MEMORY; SIGNAL GENERATION;

COST EFFECTIVENESS; DIGITAL ARITHMETIC; NETWORK PROTOCOLS;

LOGIC CIRCUITS; ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 0032283803     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (11)

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