Asynchronous pulse neural network model and its analog IC implementation

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 1998, Pages 301-304

  Horio, Yoshihiko ^a   Yasuda, Hidekazu ^a   Hanagata, Mitsuru ^a   Aihara, Kazuyuki ^a  

^a TOKYO DENKI UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS PULSE NEURAL NETWORK; EXTERNAL VOLTAGES; CMOS TECHNOLOGY; COINCIDENCE DETECTORS; NEURON CIRCUITS; NEURONAL FUNCTION; PULSE NEURAL NETWORK; SYNAPTIC DELAYS; TIME CONSTANTS;

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; LINEAR INTEGRATED CIRCUITS; MATHEMATICAL MODELS; ANALOG INTEGRATED CIRCUITS; ASYNCHRONOUS SEQUENTIAL LOGIC; NETWORKS (CIRCUITS); NEURONS;

NEURAL NETWORKS;

EID: 0032264010     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

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