GreyHound: A methodology for utilizing datapath regularity in standard design flows

Integration, the VLSI Journal

Volumn 25, Issue 2, 1998, Pages 111-135

  Nijssen, Raymond ^a   Van Eijk, Koen ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Datapath synthesis; Global placement; Logic synthesis; Regularity extraction; Structural similarity

Indexed keywords

DATA FLOW ANALYSIS; FORMAL LOGIC; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; LOGIC CIRCUITS; OPTIMIZATION;

LOGIC CORRESPONDENCE EXTRACTORS; REGULARITY EXTRACTION;

VLSI CIRCUITS;

EID: 0032203209     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(98)00010-8     Document Type: Article

References (29)

1. T. Marshburn et al., Datapath: a cmos datapath silicon assembler, Proc. ACM/IEEE Design Automation Conf., 1986, pp. 722-729.
2. R.K. Brayton, C.-L. Chen, J.A.G. Jess, R.H.J.M. Otten, L.P.P.P. vanGinneken, Wire planning for 'stackable' designs, Proc. 3rd Int. Symp. on VLSI technology, systems and applications, Taipei, ROC, 1987, pp. 269-273.
3. J.M. Kleinhans, G. Sigl, F.M. Johannes, K.J. Antreich, Gordian: Vlsi placement by quadratic programming and slicing optimization, IEEE Trans. Comput. Aided Des. 10 (3) (1991) 356-365.
4. C. Sechen, K.W. Lee, An improved simulated annealing algorithm for row-based placement, Proc. IEEE Int. Conf. on Computer-Aided Design, 1987, pp. 478-481.
5. Compass Design automation, Compass Datapath Compiler, v8r3 ed., 1991.
6. R. Leveugle, C. Safinia, Generation of optimized datapaths: bit-slice versus standard cells, IFIP Trans. A A-22 (1992) 153-66.
7. R.X.T. Nijssen, J.A.G. Jess, Two-dimensional datapath regularity extraction, Workshop notes of the 5th ACM/SIGDA Physical Design Workshop, 1996, pp. 110-117.
8. R.X.T. Nijssen, C.A.J. van Ejik, Regular layout generation of logically optimized datapaths, Proc. ACM/IEEE Int. Symp. on Physical Design, 1997, pp. 42-47.
9. G. Odawara, T. Hiraide, O. Nishina, Partitioning and placement technique for cmos gate arrays, IEEE Trans. Computer-Aided Design CAD-6 (3) (1987) 355-363.
10. H. Cai, S. Note, P. Six, H. De Man, A data path layout assembler for high performance DSP circuits, Proc. Design Automation Conf., ACM/IEEE, 1990, pp. 306-311.
11. C.E. Cheng, C.-Y. Ho, Sefop: a novel approach to data path module placement, Proc. Int. Conf. on Computer Aided Design, IEEE, New York, November 1993, pp. 178-181.
12. M. Hirsch, D. Siewiorek, Automatically extracting structure from a logical design, Proc. IEEE Int. Conf. on Computer Aided-Design, 1988, pp. 456-459.
13. K.-H. Yeap, M. Sarrafzadeh, Net-regular placement for high performance circuits, Int. J. High Speed Electron. Systems 4 (3) (1993) 245-260.
14. Y.-W. Tsay, Y.-L. Lin, A row-based cell placement method that utilizes circuit structural properties, IEEE Trans. Comput. Aided Design 14 (3) (1995) pp. 393-397.
15. T. Asano, An optimum gate placement algorithm for MOS one-dimensional arrays, J. Des. Systems 6 (1) (1982) 1-27.
16. C.M. Fiduccia, R.M. Mattheyses, A linear-time heuristic for improving network partitions, Proc. ACM/IEEE Design Automation Conference, 1982, pp. 175-181.
17. S. Goto, I. Cederbaum, B.S. Ting, Suboptimum solution of the back-board ordering with channel capacity constraint, IEEE Trans. Circuits Systems 24 (11) (1977) 645-652.
18. H. Nakao, O. Kitada, M. Hayashikoshi, K. Okazaki, Y. Tsujihashi, A high density datapath layout generation method under path delay constraints, Proc. Custom Integrated Circuits Conf., 1993, pp. 9.5.1-9.5.5.
19. D. Verkest, L. Claesen, H. De Man, Special benchmark session on formal system design, VLSI Design Methods: Proc. IFIP WG 10.2/WG 10.5 Int. Workshop on Applied Formal Methods for Correct VLSI Design, 1990, pp. 413-414.
20. D. Brand, Verification of large synthesized designs, Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, 1993, pp. 534-537.
21. W. Kunz, HANNIBAL: an efficient tool for logic verification based on recursive learning, Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, 1993, pp. 538-543.
22. C.A.J. van Eijk, Formal methods for the verification of digital circuits, Ph.D. Thesis, Eindhoven University of Technology, September 1997.
23. J. Jain, R. Mukherjee, M. Fujita, Advanced verification techniques based on learning, newblock, Proc. ACM/IEEE Design Automation Conf., 1995, pp. 420-426.
24. A. Kuehlmann, F. Krohm, Equivalence checking using cuts and heaps, Proc. ACM/IEEE Design Automation Conf., 1997, pp. 263-268.
25. Y. Matsunaga, An efficient equivalence checker for combinational circuits, Proc. ACM/IEEE Design Automation Conf., 1996, pp. 629-634.
26. S.M. Reddy, W. Kunz, D.K. Pradhan, Novel verification framework combining structural and OBDD methods in a synthesis environment, Proc. ACM/IEEE Design Automation Conf. 1995, pp. 414-419.
27. D. Stoffel, W. Kunz, Record & play: a structural fixed point iteration for sequential circuit verification, Proc. IEEE Int. Conf. on Computer-Aided Design, 1997, pp. 394-399.
28. D. Brand et al., Incremental Synthesis, Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, 1994, pp. 14-18.
29. R.E. Bryant, Graph based algorithms for Boolean function manipulation, IEEE Trans. Comput. C-35 (8) (1986) 677-691.