Pin assignment for multi-FPGA systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 9, 1997, Pages 956-964

  Hauck, Scott ^a   Borriello, Gaetano ^a  

^a Northwestern University   (United States)

Author keywords

Logic emulation; Multi fpga systems; Pin assignment; Reconfigurable computing; Routing

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; SUBSTRATES;

LOGIC EMULATION; MULTI FIELD PROGRAMMABLE GATE ARRAYS; PIN ASSIGNMENT METHODS; RECONFIGURABLE COMPUTING;

LOGIC GATES;

EID: 0031220620     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.658564     Document Type: Article

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