Comparison of GIDL in p+-poly PMOS and n+-poly PMOS Devices

IEEE Electron Device Letters

Volumn 17, Issue 6, 1996, Pages 285-287

  Lindert, Nick ^a,c   Yoshida, Makoto ^b,c   Wann, Clement ^a   Hu, Chenming ^a,c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b HITACHI LTD   (Japan)

^c IEEE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENT MEASUREMENT; ELECTRON ENERGY LEVELS; ELECTRON TUNNELING; GATES (TRANSISTOR); INTERFACES (MATERIALS); LEAKAGE CURRENTS; OXIDES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING;

BAND TO BAND TUNNELING; DRAIN STRUCTURES; GATE INDUCED DRAIN LEAKAGE; GATE OXIDES;

MOSFET DEVICES;

EID: 0030169577     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.496459     Document Type: Article

References (5)

1. T.Y.Chan, J. Chen, P. K. Ko, and C. Hu, "The impact of gate-induced-drain- leakage current on MOSFET scaling," IEDM Tech. Dig., pp. 718-721, 1987.
2. S. A. Parke, J. E. Moon, H. J. Wann, P.K. Ko, and C. Hu, "Design for suppression of gate-induced drain leakage in LDD MOSFET's using a quasi-two dimensional analytical model," IEEE Trans. Electron Devices, vol. 39, no. 7, July 1992.
3. H.J. Wann, P. K. Ko, and C. Hu, "Gate-induced band -to-band tunneling leakage current in LDD MOSFET's," IEDM Tech. Dig., pp. 147-150, 1992.
4. G. Q. Lo, A. B. Joshi, and D. L. Kwong, "Hot-carrier-stress effects on gate induced drain leakage current in n-channel MOSFET's," IEEE Electron Device Lett., vol. 12, no. 1, p. 5, Jan. 1991.
5. K. Rais, F. Balestra, G. Ghibaudo, "Temperature dependence of gate induced drain leakage current in silicon CMOS devices," Electron. Lett., vol. 30, no. 1, 1994.