Mechanical verification of adder circuits using rewrite rule laboratory

Formal Methods in System Design

Volumn 13, Issue 2, 1998, Pages 127-158

  Kapur, Deepak ^a   Subramaniam, M ^a  

^a State University of New York   (United States)

Author keywords

Automatic verification; Carry lookahead adder; Divide and conquer; Formal verification; Generic adders; Parallel prefix; Powerlists; Proof by induction; Ripple carry adder

Indexed keywords

ARRAYS; COMPUTATIONAL METHODS; DATA STRUCTURES; NETWORKS (CIRCUITS); NUMBER THEORY; PARALLEL ALGORITHMS; RECURSIVE FUNCTIONS; SET THEORY; THEOREM PROVING; ALGORITHMS; CARRY LOGIC; COMPUTATIONAL COMPLEXITY; FORMAL LOGIC;

AUTOMATIC VERIFICATION; CARRY LOOKAHEAD ADDER; DIVIDE AND CONQUER; FORMAL VERIFICATION; GENERIC ADDERS; PARALLEL PREFIX; POWERLISTS; PROOF BY INDUCTION; RIPPLE CARRY ADDER; CARRY LOOKAHEAD ADDERS; FORMAL VERIFICATION METHODS; RIPPLE CARRY ADDERS;

ADDERS;

EID: 0032165446     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008610818519     Document Type: Article

References (44)

1. C.M. Angelo, L. Claesen, and H. De Man. A Methodology for proving correctness of parameterized hardware modules in HOL, , CHDL '91, (eds. D. Borrione and R. Waxman), Elsevier Science Publishers B. V. (North-Holland), Amsterdam, 1991.
2. C.M. Angelo. Formal Hardware Verification in a Silicon Compilation Environment by Means of Theorem Proving. Ph.D. Thesis, IMEC / Katholieke Universiteit Leuven, Belgium, February 1994.
3. W. Adams. Verifying adder circuits using powerlists, University of Texas at Austin, CS. Dept Tech. Report, CS-TR-94-02, 1994.
4. D.A. Basin and N. Klarlund. Hardware verification using monadic second-order logic. Mathematical Induction Workshop, Dagsruhl, Germany, Aug. 1995.
5. R.S. Boyer and J S. Moore. A Computational Logic Handbook. Academic Press, New York, 1988.
6. R.P. Brent and H.T. Kung. A regular layout for parallel adders. In E. E. Swartzlander, editor, Computer Arithmetic, Volume 11. IEEE Computer Society Press, 1990.
7. R.E. Bryant. Graph-based Algorithms for boolean function manipulation", IEEE transactions on Computers, C-35, 1986.
8. R.E. Bryant, and Y.-A. Chen. Verification of arithmetic functions with binary moment diagrams. Technical Report CMU-CS-94-160, Carnegie Mellon University, June 1994.
9. J.R. Burch, E.M. Clarke, K. L. Mcmillan and D.L. Dill. Sequential circuit verification using symbolic model checking. In Proc. 27th ACM/IEEE Design Automation Conference, 1990.
10. A.J. Camilleri, M.J.C. Gordon and T.F.Melham. Hardware verification using higher-order logic. In D. Borrione, editor, HDL Descriptions to Guaranteed Correct Circuit Designs. North-Holland, Amsterdam 1987, pages 43-67.
11. E.M. Clarke, S.M. German and X. Zhao. Verifying the SRT division algorithm using theorem proving techniques. In Proc. Computer Aided Verification, 8th Intl. Conf. - CAV'96, volume 1102 of Lecture Notes in Computer Science, New Brunswick, July/August 1996, pages 111-122.
12. A.J. Cohn. A proof of Correctness of the Viper microprocessors: The first level. In G. Birtwistle and P. A. Subrahmanyam, editors, VLSI Specification, Verification and Synthesis, Kluwer Academic Publishers, Boston, 1992, pages 27-72.
13. T.H. Cormen, C.E. Leiserson, and R.L. Rivest. Introduction to Algorithms. MIT Press, 1991.
14. nd Conf. on Theorem Provers in Circuit Design, September 1994.
15. B C. Brock, W.A. Hunt and M. Kaufmann. The FM9001 microprocessor proof. Technical Report 86, CLI, December 1994.
16. A. Gupta and A.L. Fisher. Parametric circuit representation using inductive boolean functions. In C. Courcoubetis, editor, em Proc. Computer Aided Verification, volume 697 of Lecture Notes in Computer Science, Springer, Berlin, 1993.
17. W.A. Hunt and B.C. Brock. The Verification of a bit-slice ALU. Proc. Workshop on Hardware Specification. Verification and Synthesis: Mathematical Aspects, volume 408 of Lecture Notes in Computer Science, Springer, Berlin, 1989.
18. W.A. Hunt. Jr. FM8501: A Verified Microprocessor. Ph.D thesis, University of Texas at Austin, 1985.
19. V. Stavridou, T.F. Melham and R.T.Boute, editors. Theorem Provers in Circuit Design, IFIP Transactions. North-Holland, 1992.
20. L.C. Paulson. The foundations of a generic theorem prover. Journal of Automated Reasoning, 5, 1989.
21. J. Joyce, G. Birtwistle and M. Gordon. Proving a computer correct in HOL. Technical Report 100, Computer Lab. University of Cambridge, 1986.
22. D. Kapur. Constructors can be partial too. In R. Veroff, editor, Essays in Honor of Larry Was. MIT Press, Cambridge, MA, 1996.
23. D. Kapur. Automated tools for analyzing completeness of specifications. In Proc. 1994 Intl. Symp. on Software Testing and Analysis (ISSTA), Seattle, WA, August 1994, pages 28-43.
24. D. Kapur. Rewriting, decision procedures and lemma speculation for automated hardware verification. Invited Talk. In Proc. Theorem Provers in Higher-order Logics, New Jersey, August 1997.
25. D. Kapur and D.R. Musser. Tecton: A framework for specifying and verifying generic system components. Invited Talk. In TPCD Conf. 1992 (Theorem Provers in Circuit Design), University of Nijmegen, Netherlands, June 1992.
26. D. Kapur, D.R. Musser and X. Nie. An Overview of the Tecton proof system, Theoretical Computer Science Journal, 133:307-339, October 1994.
27. D. Kapur and X. Nie. Reasoning about numbers in Tecton. In Proc. 8th Intl. Symp. Methodologies for Intelligent Systems, (ISMIS'94), Charlotte, North Carolina, October 1994, pages 57-70.
28. D. Kapur and M. Subramaniam. Automated reasoning about parallel algorithms using powerlists. In V.S. Alagar, editor, Proc. AMAST'95, Springer, July 1995.
29. D. Kapur and M. Subramaniam. Mechanically verifying a family of multiplier circuits. In Proc. Computer Aided Verification (CAV'96), volume 1102 of Lecture Notes in Computer Science, Springer, Berlin, 1996, pages 135-146.
30. D. Kapur, and H. Zhang. An overview of Rewrite Rule Laboratory (RRL). Journal of Computer and Mathematics with Applications, 29:91-114, 1995.
31. C. A. Mead and L.A. Conway. Introduction to VLSI Systems. Addison-Wesley, Reading MA, 1980.
32. J. Misra. Powerlist: A structure for parallel recursion. In A Classical Mind: Essays in Honor of C.A.R. Hoare. Prentice Hall, January 1994. Also in TOPLAS, November 1994.
33. P. Narendran and J. Stillman. Hardware verification in the interactive VHDL workstation. In G. Birtwistle and P.A. Subrahmanyam, editors, VLSI Specification, Verification, and Synthesis. Kluwer Academic Publishers, Boston, 1988, pages 235-255.
34. P. Narendran and J. Stillman. Formal verification of the Sobel image processing chop. In Proc. Design Automation, 1988.
35. W. Pratt. Digital Image Processing. John Wiley & Sons, Inc., 1978.
36. M. Sheeran and G. Jones. Circuit design in Ruby. In J. Staunstrup, editor, Formal Methods for VLSI Design. Elsevier, 1990.
37. L. Rossen. Ruby Algebra. In G. Jones and M. Sheeran, editors, Designing Correct Circuits. Springer-Verlag, 1990.
38. M. Srivas and M. Bickford. Formal Verification of a pipelined microprocessor. IEEE Software, September 1990.
39. M. Subramaniam. Failure Analyses of Induction Theorem Provers. Ph.D Thesis, SUNY at Albany, September 1996.
40. D. Verkest, L. Claesen and H. De Man. Correctness Proofs of Parameterized Hardware Modules in the Cathedral-II Synthesis Environment. In EDAC'90, Glasgow, Scotland, March 1990.
41. D. Verkest, L. Claesen and H. De Man. On the Use of the Boyer-Moore Theorem Prover for Correctness Proofs of Parameterized Hardware Modules. In L. Claeson, editor, Formal VLSI Specification and Synthesis: VLSI Design Methods I. Elsevier Science Publishers B. V. (North-Holland), 1990.
42. N. Vasanthavada, R. Baker and N. Kanopoulos. A monolithic image edge detection filter. In Proc. IEEE Custom Integrated Circuits Conference, 1987.
43. H. Zhang, D. Kapur and M.S. Krishnamoorthy. A mechanizable induction principle for equational specifications. In Proc. 9th Intl. Conf. Automated Deduction (CADE), volume 310 of Lecture Notes in Computer Science, Springer-Verlag, Berlin, pages 250-265, 1988.
44. H. Zhang, Implementing contextual rewriting. Proc. Third International Workshop on Conditional Term Rewriting Systems, volume 665 of Lecture Notes in Computer Science, Springer-Verlag, Berlin, pages 363-377, 1992.