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Volumn E81-C, Issue 9, 1998, Pages 1391-1396
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Processor pipeline design for fast network message handling in RWC-1 multiprocessor
a a b b c |
Author keywords
Loosely coupled multiprocessor; Massively parallel computer; Multi threaded execution; Processor pipeline; Super scalar processor
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Indexed keywords
COMPUTER ARCHITECTURE;
COMPUTER NETWORKS;
PARALLEL PROCESSING SYSTEMS;
MULTITHREADED EXECUTION;
REDUCED INTER-PROCESSOR COMMUNICATION ARCHITECTURE (RICA);
PIPELINE PROCESSING SYSTEMS;
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EID: 0032156559
PISSN: 09168524
EISSN: None
Source Type: Journal
DOI: None Document Type: Article |
Times cited : (1)
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References (6)
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