New XOR/XNOR and full adder circuits for low voltage, low power applications

Microelectronics Journal

Volumn 29, Issue 8, 1998, Pages 509-517

  Lee, Hanho ^a   Sobelman, Gerald E ^a  

^a University of Minnesota   (United States)

Author keywords

Full adder circuits; Full voltage swing; Threshold voltage; XNOR; XOR

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC LOSSES; LOGIC CIRCUITS; LOGIC DESIGN; TECHNOLOGY; THRESHOLD VOLTAGE;

FULL ADDER CIRCUITS; FULL VOLTAGE SWING;

ADDERS;

EID: 0032142461     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/s0026-2692(97)00120-1     Document Type: Article

References (7)

1. A. Chandrakasan, S. Sheng, R. Brodersen, Low-power CMOS digital design, IEEE Journal of Solid-State Circuits April (1992) 473-484.
2. U. Ko, P.T. Balsara, W. Lee, Low-power designs techniques for high-performance CMOS adders, IEEE Transactions on VLSI Systems 3 (2) (1995) 327-332.
3. M. Suzuki, K. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, A 1.5-ns 32-b CMOS ALU in double pass-transistor logic, IEEE Journal of Solid-State Circuits 28 (1995) 1145-1151.
4. N. Zhuang, H. Wu, A new design of the CMOS full adder, IEEE Journal of Solid-State Circuits May (1992) 840-844.
5. J. Wang, S. Fang, W. Feng, New efficient designs for XOR and XNOR functions on the transistor level, IEEE Journal of Solid-State Circuits 29 (7) (1994) 780-786.
6. Meta-Software, HSPICE User's Manual version H9002, Meta-Software, Inc., Campbell, CA, 1992.
7. Abu-Shama, E., Bayoumi, M., A new cell or low power adders, in: Proc. of IEEE International Symposium on Circuits and Systems, Vol. 4, 1996, pp. 49-52.