A 1.3-GHz SOI CMOS test chip for low-power high-speed pulse processing

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 8, 1998, Pages 1259-1261

  Berger, Robert ^a   Lyons, W Gregory ^a   Soares, Antonio ^a  

^a MIT LINCOLN LABORATORY   (United States)

Author keywords

CMOS; Compressive receiver; Digital signal processor; High speed self test; SOI

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; PERFORMANCE; SIGNAL RECEIVERS; SILICON ON INSULATOR TECHNOLOGY; TESTING;

PULSE PROCESSING;

MICROPROCESSOR CHIPS;

EID: 0032137984     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.705366     Document Type: Article

References (5)

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