SCOPUS 정보 검색 플랫폼 - 논문 보기

메뉴 건너뛰기

IEEE Design and Test of Computers

Volumn 15, Issue 3, 1998, Pages 77-82

Pentium pro processor design for test and debug

(2) Carbine, Adrian a,b,c,d Feltham, Derek a,e,f

a INTEL CORPORATION (United States)

b Intel ^* (United States)

c BRIGHAM YOUNG UNIVERSITY (United States)

d IEEE (United States)

e UNIVERSITY OF TORONTO (Canada)

f CARNEGIE MELLON UNIVERSITY (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER DEBUGGING; COMPUTER HARDWARE; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

DESIGN FOR TEST (DFT) METHOD;

MICROPROCESSOR CHIPS;

EID: 0032121301 PISSN: 07407475 EISSN: None Source Type: Journal
DOI: 10.1109/54.706037 Document Type: Article

Times cited : (25)

References (10)

1
- 0029256210
- A 0.6um BiCMOS Processor with Dynamic Execution
- IEEE, Piscataway, N.J., Feb
- R. Colwell and R. Steck, "A 0.6um BiCMOS Processor with Dynamic Execution," Digest of Tech. Papers, Int'l Solid-State Circuits Conf., IEEE, Piscataway, N.J., Feb 1995, pp. 176-177.
- (1995) Digest of Tech. Papers, Int'l Solid-State Circuits Conf. , pp. 176-177
- Colwell, R.¹ Steck, R.²

2
- 84889222999
- Intel Pentium II Processor Web page, http://www.intel.com/ pentiumll/home.htm.

3
- 0030737063
- Designing UltraSparc for Testability
- Jan.-Mar.
- M. Levitt, "Designing UltraSparc for Testability," IEEE Design & Test of Computers, Vol. 14, No. 1, Jan.-Mar. 1997, pp. 10-17.
- (1997) IEEE Design & Test of Computers , vol.14 , Issue.1 , pp. 10-17
- Levitt, M.¹

4
- 0030736471
- Alpha 21164 Testability Strategy
- Jan.-Mar.
- D. Bhavsar and J. Edmondson, "Alpha 21164 Testability Strategy," IEEE Design & Test of Computers, Vol. 14, No. 1, Jan.-Mar. 1997, pp. 25-33.
- (1997) IEEE Design & Test of Computers , vol.14 , Issue.1 , pp. 25-33
- Bhavsar, D.¹ Edmondson, J.²

5
- 0001844347
- Testability Features of the MC68060 Microprocessor
- IEEE Computer Society Press, Los Alamitos, Calif.
- A. Crouch, M. Pressly, and J. Circello, "Testability Features of the MC68060 Microprocessor," Proc. IEEE Int'l Test Conf., IEEE Computer Society Press, Los Alamitos, Calif., 1994, pp. 60-69.
- (1994) Proc. IEEE Int'l Test Conf. , pp. 60-69
- Crouch, A.¹ Pressly, M.² Circello, J.³

6
- 0011882870
- Balancing Structured and Ad-Hoc Design for Test: Testing the PowerPC 603™ Microprocessor
- IEEE CS Press
- C. Hunter, E. Vida-Torku, and J. LeBlanc, "Balancing Structured and Ad-Hoc Design for Test: Testing the PowerPC 603™ Microprocessor," Proc. IEEE Int;l Test Conf., IEEE CS Press, 1994, pp. 76-83.
- (1994) Proc. IEEE Int;l Test Conf. , pp. 76-83
- Hunter, C.¹ Vida-Torku, E.² LeBlanc, J.³

7
- 0027799159
- Test Features of the HP PA7100LC Processor
- IEEE CS Press
- D. Josephson, D. Dixon, and B. Arnold, "Test Features of the HP PA7100LC Processor," Proc. IEEE Int'l Test Conf., IEEE CS Press, 1993, pp. 764-772.
- (1993) Proc. IEEE Int'l Test Conf. , pp. 764-772
- Josephson, D.¹ Dixon, D.² Arnold, B.³

8
- 85008063226
- Intel and the Myths of Test
- Spring
- K. Thompson, "Intel and the Myths of Test," IEEE Design & Test of Computers, Vol. 13, No. 1, Spring 1996, pp. 79-81.
- (1996) IEEE Design & Test of Computers , vol.13 , Issue.1 , pp. 79-81
- Thompson, K.¹

9
- 0003415191
- (includes IEEE Std 1149. 1a-1993), IEEE
- IEEE Std. 1149.1-1990, Standard Test Access Port and Boundary-Scan Architecture, (includes IEEE Std 1149. 1a-1993), IEEE, 1993.
- (1993) IEEE Std. 1149.1-1990, Standard Test Access Port and Boundary-Scan Architecture

10
- 84889199170
- "Scan Mechanism for Monitoring the State of Internal Signals of a VLSI Microprocessor Chip," US Patent No. 5,253,255
- A. Carbine, "Scan Mechanism for Monitoring the State of Internal Signals of a VLSI Microprocessor Chip," US Patent No. 5,253,255.
- Carbine, A.¹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.