-
1
-
-
0004219960
-
Random Graphs
-
New York: Academic
-
B. Bollobas, Random Graphs. New York: Academic, 1985, pp. 11–12, 31–53.
-
-
-
Bollobas, B.1
-
3
-
-
85069387521
-
Efficient partitioning of components
-
July
-
H. R. Charney and D. L. Plato, “Efficient partitioning of components,” IEEE Design Automation, pp. 16.0-16.21, July 1968.
-
(1968)
IEEE Design Automation
, pp. 16.0-16.21
-
-
Charney, H.R.1
Plato, D.L.2
-
4
-
-
84909710009
-
Maximum concurrent flow and minimum ratio cut
-
Dec.
-
C. K. Cheng and T. C. Hu, “Maximum concurrent flow and minimum ratio cut,” Tech. Rep. CS88-141, Dec., 1988.
-
(1988)
Tech. Rep. CS88-141
-
-
Cheng, C.K.1
Hu, T.C.2
-
5
-
-
0004139889
-
Linear Programming
-
San Francisco, CA: Freeman
-
V. Chvatal, Linear Programming. San Francisco, CA: Freeman, 1983.
-
(1983)
-
-
Chvatal, V.1
-
6
-
-
0000359078
-
Simultaneous floor planning and global routing for hierarchical building-block layout
-
W. M. Dai and E. S. Kuh, “Simultaneous floor planning and global routing for hierarchical building-block layout,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 828–837, 1987.
-
(1987)
IEEE Trans. Computer-Aided Design
, vol.CAD-6
, pp. 828-837
-
-
Dai, W.M.1
Kuh, E.S.2
-
7
-
-
0041977585
-
Logic partitioning
-
B. Preas and M. Lorenzetti, ed. Menlo Park, CA: Benjamin/Cummings
-
W. E. Donath, “Logic partitioning,” in Physical Design Automation of VLSI Systems, B. Preas and M. Lorenzetti, ed. Menlo Park, CA: Benjamin/Cummings, 1988, pp. 65–86.
-
(1988)
Physical Design Automation of VLSI Systems
, pp. 65-86
-
-
Donath, W.E.1
-
9
-
-
84957946170
-
Flows in Networks
-
Princeton, NJ: Princeton University
-
L. R. Ford and D. R. Fulkerson, Flows in Networks. Princeton, NJ: Princeton University, 1962.
-
(1962)
-
-
Ford, L.R.1
Fulkerson, D.R.2
-
12
-
-
4243132003
-
On an extension of the maximum flow minimum cut theorem to multicommodity flows
-
Dec.
-
M. Iri, “On an extension of the maximum flow minimum cut theorem to multicommodity flows,” J. Oper. Res. Soc. Japan, vol. 5, no. 4, pp. 697–703, Dec. 1967.
-
(1967)
J. Oper. Res. Soc. Japan
, vol.5
, Issue.4
, pp. 697-703
-
-
Iri, M.1
-
13
-
-
84990479742
-
An efficient heuristic procedure for partitioning graphs
-
Feb.
-
B. W. Kemighan and S. Lin, “An efficient heuristic procedure for partitioning graphs,” Bell Syst. Tech. J., vol. 49, no. 2, pp. 291–307, Feb. 1970.
-
(1970)
Bell Syst. Tech. J
, vol.49
, Issue.2
, pp. 291-307
-
-
Kemighan, B.W.1
Lin, S.2
-
14
-
-
26444479778
-
Optimization by simulated annealing
-
S. Kirkpatrick, C. D. Gelatt, Jr., and M. P. Vecchi, “Optimization by simulated annealing,” Sci., vol. 220, pp. 671–680, 1983.
-
(1983)
Sci.
, vol.220
, pp. 671-680
-
-
Kirkpatrick, S.1
Gelatt, C.D.2
Vecchi, M.P.3
-
15
-
-
0021425044
-
An improved min-cut algorithm for partitioning VLSI networks
-
May
-
B. Krishnamurthy, “An improved min-cut algorithm for partitioning VLSI networks,” IEEE Trans. Comput., vol. C-33, pp. 438–446, May 1984.
-
(1984)
IEEE Trans. Comput.
, vol.C-33
, pp. 438-446
-
-
Krishnamurthy, B.1
-
17
-
-
0020591653
-
Computer-aided partitioning of behavioral hardware description
-
M. C. McFarland, “Computer-aided partitioning of behavioral hardware description,” in Proc. 20th Design Automation Conf., 1983, pp. 474–478.
-
(1983)
Proc. 20th Design Automation Conf.
, pp. 474-478
-
-
McFarland, M.C.1
-
18
-
-
0015095649
-
On feasibility conditions of multicommodity flows in networks
-
K. Onaga and O. Kakusho, “On feasibility conditions of multicommodity flows in networks,” IEEE Trans. Circuit Theory, vol. CT-18, pp. 425–429, 1971.
-
(1971)
IEEE Trans. Circuit Theory
, vol.CT-18
, pp. 425-429
-
-
Onaga, K.1
Kakusho, O.2
-
19
-
-
0024481167
-
Multi-way network partitioning
-
Jan.
-
L. A. Sanchis, “Multi-way network partitioning,” IEEE Trans. Comput., vol. 38, pp. 62–81, Jan. 1989.
-
(1989)
IEEE Trans. Comput.
, vol.38
, pp. 62-81
-
-
Sanchis, L.A.1
-
22
-
-
0024178684
-
An improved objective function for mincut circuit partitioning
-
C. Sechen and D. Chen, “An improved objective function for mincut circuit partitioning,” in Proc. Int. Conf. on Computer-Aided Design, 1988, pp. 502–505.
-
(1988)
Proc. Int. Conf. on Computer-Aided Design
, pp. 502-505
-
-
Sechen, C.1
Chen, D.2
-
23
-
-
79955051578
-
Fast heuristic techniques for placing and wiring printed circuit boards
-
Comp. Sci. Dep. Univ. Illinois
-
J. E. Stevens, “Fast heuristic techniques for placing and wiring printed circuit boards,” Ph.D. dissertation, Comp. Sci. Dep. Univ. Illinois, 1972.
-
(1972)
Ph.D. dissertation
-
-
Stevens, J.E.1
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