Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area

Solid-State Electronics

Volumn 42, Issue 6, 1998, Pages 1007-1014

  Ker, Ming Dou ^a   Wu, Chung Yu ^a   Huang, Chien Chang ^a   Chen, Tung Yang ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTING SILICON; TRANSISTORS;

OPTICAL TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 0032090717     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(98)00112-9     Document Type: Article

References (7)

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5. Beebe, S. G., EOS/ESD Symp. Proc., 1996, EOS-18, 265.
6. Ker, M.-D., Huang, C.-C. and Wu, C.-Y., Int. Electron Devices and Materials Symp. Proc., 1996, p. 181.
7. Ker, M.-D. and Wu, T.-S., IEDM Tech. Dig., 1996, p. 889.