A low temperature silicon-on-insulator fabrication process using Si MBE on double-layer porous silicon

Journal of the Electrochemical Society

Volumn 145, Issue 5, 1998, Pages 1668-1671

  Zheng, D W ^a   Cui, Q ^a   Huang, Y P ^c   Zhang, X J ^a   Kwor, R ^b   Li, A Z ^a   Tang, T A ^a  

^a FUDAN UNIVERSITY   (China)

^b University of Colorado at Colorado Springs   (United States)

^c NONE

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; ANODIC OXIDATION; CRYSTAL IMPURITIES; CRYSTAL MICROSTRUCTURE; LOW TEMPERATURE OPERATIONS; MOLECULAR BEAM EPITAXY; POROUS SILICON; SEMICONDUCTOR DOPING; SILICON WAFERS; SURFACE CLEANING; THERMOOXIDATION;

TWO STEP ANODIZATION;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0032075662     PISSN: 00134651     EISSN: None     Source Type: Journal    
DOI: 10.1149/1.1838535     Document Type: Article

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