Stacked quantum dot transistor and charge-induced confinement enhancement

Electronics Letters

Volumn 34, Issue 10, 1998, Pages 1030-1031

  Guo, L J ^a   Chou, S Y ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CHARGE; ELECTRIC CONDUCTIVITY OF SOLIDS; GATES (TRANSISTOR); OSCILLATIONS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE;

FLOATING GATES;

SEMICONDUCTOR QUANTUM DOTS;

EID: 0032074085     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19980717     Document Type: Article

References (7)

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2. YANO, K., ISHII, T., HASHIMOTO, T., KOBAYASHI, T., MURAI, F., and SEKI, K.: 'A room temperature single-electron memory device using fine-grain polycrystalline silicon'. IEDM Tech. Dig., 1993, pp. 541-544
3. GUO, L.J., LEOBANDUNG, E., and CHOU, S.Y.: 'A silicon single-electron transistor memory operating at room temperature'. Science, 1997, 275, (5300), pp. 649-651
4. LEOBANDUNG, E., GOU, L.J., and CHOU, S.Y.: 'Electron and hole silicon quantum dot transistors operating above 100 K', J. Vac. Sci. Technol. B. 1995, 13, (6), pp. 2865-2868
5. GRABET, H., and DEVORET, M.H.: 'Single charge tunneling: Coulomb blockade phenomena in nanostructures' (Plenum, New York, 1992)
6. BEENAKKER, C.W.J.: 'Theory of Coulomb-blockade oscillations in the conductance of a quantum dot', Phys. Rev. B, 1991, 44, pp. 1646-1656
7. BALESTRA, F., CRISTOLOVEANU, S., BENACHIR, M., BRINI, J., and ELEWA, T.: 'Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance', IEEE Electron Device Lett., 1987, EDL-8, (9), pp. 410-412