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Volumn E81-B, Issue 5, 1998, Pages 910-918

Performance analysis of weighted round robin cell scheduling and its improvement in ATM networks

Author keywords

ATM; Burstiness; Delay bound; Scheduler; Weighted round robin

Indexed keywords

BANDWIDTH; CONGESTION CONTROL (COMMUNICATION); ELECTRIC NETWORK ANALYSIS; QUEUEING THEORY; TELECOMMUNICATION TRAFFIC;

EID: 0032068306     PISSN: 09168516     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (12)

References (11)
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  • 3
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    • Parekh, A.K.1    Gallager, R.G.2
  • 4
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    • A generalized processor sharing approach to flow control in integrated services networks: The multiple node case
    • A.K. Parekh and R.G. Gallager, "A generalized processor sharing approach to flow control in integrated services networks: The multiple node case," IEEE/ACM Trans. Networking, vol.2, no.2, pp.137-150, 1994.
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    • Parekh, A.K.1    Gallager, R.G.2
  • 5
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    • A self-clocked fair queueing scheme for broadband applications
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    • Golestani, S.J.1
  • 6
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    • Roberts, J.W.1
  • 7
    • 0030087197 scopus 로고    scopus 로고
    • Bandwidth scheduling for wide-area ATM networks using virtual finishing times
    • A. Hunh and G. Kesidis, "Bandwidth scheduling for wide-area ATM networks using virtual finishing times," IEEE/ACM Trans. Networking, vol.4, no.1, pp.643-641, 1996.
    • (1996) IEEE/ACM Trans. Networking , vol.4 , Issue.1 , pp. 643-1641
    • Hunh, A.1    Kesidis, G.2
  • 8
    • 0029778714 scopus 로고    scopus 로고
    • Hardware-efficient fair queueing architectures for high-speed networks
    • J. Rexford, A.G. Greenberg, and F.G. Bonomi, "Hardware-efficient fair queueing architectures for high-speed networks," Proc. IEEE INFOCOM '96, pp.638-646, 1996.
    • (1996) Proc. IEEE Infocom '96 , pp. 638-646
    • Rexford, J.1    Greenberg, A.G.2    Bonomi, F.G.3
  • 9
    • 0026243589 scopus 로고
    • Weighted round-robin cell multiplexing in a general-purpose ATM switch chip
    • M. Katavenis, S. Sidiropoulos, and C. Courcoubetis, "Weighted round-robin cell multiplexing in a general-purpose ATM switch chip," IEEE J. Sel. Areas Commun., vol.9, no.8, 1991.
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    • Katavenis, M.1    Sidiropoulos, S.2    Courcoubetis, C.3
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    • Latency-rate servers: A general model for analysis in traffic scheduling algorithms
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    • Stiliadis, D.1    Varma, A.2
  • 11
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    • A Single-Chip Controller for 1.2Gbps Shared Buffer ATM Switches
    • N. Mizukoshi, R. Fan, H. Suzuki, and M. Shinohara, "A Single-Chip Controller for 1.2Gbps Shared Buffer ATM Switches," Proc. CICC, pp.449-452, 1997.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.