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Volumn 145, Issue 2, 1998, Pages 127-133

Design for the discrete cosine transform in VLSI

Author keywords

Discrete cosine transform; Image compression

Indexed keywords

ALGORITHMS; FREQUENCY DOMAIN ANALYSIS; IMAGE COMPRESSION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL TRANSFORMATIONS; MULTIPLYING CIRCUITS; OPTIMIZATION;

EID: 0032027277     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19981911     Document Type: Article
Times cited : (8)

References (29)
  • 1
    • 0026142897 scopus 로고
    • The JPEG still picture compression standard
    • April
    • WALLACE, G.K.: 'The JPEG still picture compression standard', Commun. ACM, April 1991, 3-4, pp. 31-44
    • (1991) Commun. ACM , vol.3-4 , pp. 31-44
    • Wallace, G.K.1
  • 3
    • 0026137432 scopus 로고
    • MPEG: A video compression standard for multi-media applications
    • April
    • GALL, D.L.: 'MPEG: a video compression standard for multi-media applications', Commun. ACM, April 1991, 3-4, pp. 46-58
    • (1991) Commun. ACM , vol.3-4 , pp. 46-58
    • Gall, D.L.1
  • 8
    • 0017538003 scopus 로고
    • A fast computation algorithm for the discrete cosine transform
    • CHEN, W., SMITH, C.H., and FRALICK, S.: 'A fast computation algorithm for the discrete cosine transform', IEEE Trans. Commun., 1977, 25, pp. 1004-1009
    • (1977) IEEE Trans. Commun. , vol.25 , pp. 1004-1009
    • Chen, W.1    Smith, C.H.2    Fralick, S.3
  • 10
    • 0000276706 scopus 로고
    • A fast DCT-SQ scheme for images
    • ARAI, Y., AGUI, T., and NAKAJIMA, M.: 'A fast DCT-SQ scheme for images', Trans. IEICE, 1988, E71, pp. 1095-1097
    • (1988) Trans. IEICE , vol.E71 , pp. 1095-1097
    • Arai, Y.1    Agui, T.2    Nakajima, M.3
  • 11
    • 0029291183 scopus 로고
    • New systolic array implementation of the 2-D discrete cosine transform and its inverse
    • CHANG, Y.T., and WANG, C.L.: 'New systolic array implementation of the 2-D discrete cosine transform and its inverse', IEEE Trans. Circuits Syst. Video Technol, 1995, 5, pp. 150-157
    • (1995) IEEE Trans. Circuits Syst. Video Technol , vol.5 , pp. 150-157
    • Chang, Y.T.1    Wang, C.L.2
  • 12
    • 0027556384 scopus 로고
    • Unified parallel lattice structures for time-recursive discrete cosine/sine/hartley transforms
    • RAY-LIU, K., and CHIU, C.T.: 'Unified parallel lattice structures for time-recursive discrete cosine/sine/hartley transforms', IEEE Trans. Signal Process., 1993, 41, pp. 1357-1377
    • (1993) IEEE Trans. Signal Process. , vol.41 , pp. 1357-1377
    • Ray-Liu, K.1    Chiu, C.T.2
  • 13
    • 0026837632 scopus 로고
    • Real-time parallel and fully pipelined two-dimensional DCT lattice structures with application to HDTV systems
    • CHIU, C.T., and RAY-LIU, K.: 'Real-time parallel and fully pipelined two-dimensional DCT lattice structures with application to HDTV systems', IEEE Trans. Circuits Syst. Video Technol., 1992, 2, pp. 25-37
    • (1992) IEEE Trans. Circuits Syst. Video Technol. , vol.2 , pp. 25-37
    • Chiu, C.T.1    Ray-Liu, K.2
  • 15
    • 0030083342 scopus 로고    scopus 로고
    • VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications
    • SRINIVASAN, V., and RAY-LIU, K.: 'VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications', IEEE Trans. Circuits Syst. Video Technol., 1996, 6, pp. 87-96
    • (1996) IEEE Trans. Circuits Syst. Video Technol. , vol.6 , pp. 87-96
    • Srinivasan, V.1    Ray-Liu, K.2
  • 16
    • 84999115011 scopus 로고
    • Full custom VLSI implementation of high-speed 2-D DCT/IDCT chip
    • November
    • SRINIVASAN, V., and RAY-LIU, K.: 'Full custom VLSI implementation of high-speed 2-D DCT/IDCT chip.' IEEE Proceedings ICIP-94, November 1994, Vol. 3, pp. 606-610
    • (1994) IEEE Proceedings ICIP-94 , vol.3 , pp. 606-610
    • Srinivasan, V.1    Ray-Liu, K.2
  • 17
    • 0029359214 scopus 로고
    • Computation of discrete cosine transform using Clenshaw's recurrence formula
    • ABURDENE, M.F., ZHENG, J., and KOZICK, R.J.: 'Computation of discrete cosine transform using Clenshaw's recurrence formula', IEEE Signal Process. Lett., 1995, 2, pp. 155-156
    • (1995) IEEE Signal Process. Lett. , vol.2 , pp. 155-156
    • Aburdene, M.F.1    Zheng, J.2    Kozick, R.J.3
  • 19
    • 0029388830 scopus 로고
    • VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor
    • HSIA, S.C., LIU, B.D., YANG, J.F., and BAI, B.L.: 'VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor', IEEE Trans. Circuits Syst. Video Technol. 1995, 5, pp. 396-406
    • (1995) IEEE Trans. Circuits Syst. Video Technol. , vol.5 , pp. 396-406
    • Hsia, S.C.1    Liu, B.D.2    Yang, J.F.3    Bai, B.L.4
  • 21
    • 0028407773 scopus 로고
    • Novel VLSI implementation of (8 × 8) point 2-D DCT
    • MCGOVERN, F.A., WOODS, R.F., and VAN, M.: 'Novel VLSI implementation of (8 × 8) point 2-D DCT', Electron. Lett., 1994, 30, pp. 624-626
    • (1994) Electron. Lett. , vol.30 , pp. 624-626
    • Mcgovern, F.A.1    Woods, R.F.2    Van, M.3
  • 22
    • 0026925543 scopus 로고
    • Fast algorithms for the discrete cosine transform
    • FEIG, E., and WINOGRAD, S.: 'Fast algorithms for the discrete cosine transform', IEEE Trans. Signal Process., 1992, 40, pp. 2174-2193
    • (1992) IEEE Trans. Signal Process. , vol.40 , pp. 2174-2193
    • Feig, E.1    Winograd, S.2
  • 24
    • 0029246894 scopus 로고
    • JAGUAR: A fully pipelined VLSI architecture for JPEG imace compression standard
    • KOVAC, M., and RANGANATHAN, N.: 'JAGUAR: a fully pipelined VLSI architecture for JPEG imace compression standard', Proc. IEEE, 1995, 83, pp. 247-257
    • (1995) Proc. IEEE , vol.83 , pp. 247-257
    • Kovac, M.1    Ranganathan, N.2
  • 25
    • 0029308478 scopus 로고
    • A low ROM distributed arithmetic implementation of the forward/inverse DCT/DST using rotations
    • KARATHANASIS, H.C.: 'A low ROM distributed arithmetic implementation of the forward/inverse DCT/DST using rotations', IEEE Trans. Consum. Electron., 1995, 41, pp. 263-272
    • (1995) IEEE Trans. Consum. Electron. , vol.41 , pp. 263-272
    • Karathanasis, H.C.1
  • 26
    • 0023330761 scopus 로고
    • CMOS differential pass-transistor locic desien
    • PASTERNAK, J., and SHUBAT, A.: 'CMOS differential pass-transistor locic desien', IEEE J. Solid-State Circuits, 1987, SSC-22, pp. 216-222
    • (1987) IEEE J. Solid-State Circuits , vol.SSC-22 , pp. 216-222
    • Pasternak, J.1    Shubat, A.2
  • 27
    • 0029388046 scopus 로고
    • VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding
    • MASAKI, T., MORIMOTO, Y., ONOYE, T., and SHIRAKAWA, I.: 'VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding', IEEE Trans. Circuits Syst. Video Technol., 1995, 5, pp. 387-395
    • (1995) IEEE Trans. Circuits Syst. Video Technol. , vol.5 , pp. 387-395
    • Masaki, T.1    Morimoto, Y.2    Onoye, T.3    Shirakawa, I.4
  • 28
    • 33746143351 scopus 로고
    • A novel architecture for VLSI implementation of the 2-D DCT/IDCT
    • CUCCHI, S., and FRATTI, M.: 'A novel architecture for VLSI implementation of the 2-D DCT/IDCT, IEEE, 1992, V, pp. 693-696
    • (1992) IEEE , vol.V , pp. 693-696
    • Cucchi, S.1    Fratti, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.