-
1
-
-
0026142897
-
The JPEG still picture compression standard
-
April
-
WALLACE, G.K.: 'The JPEG still picture compression standard', Commun. ACM, April 1991, 3-4, pp. 31-44
-
(1991)
Commun. ACM
, vol.3-4
, pp. 31-44
-
-
Wallace, G.K.1
-
3
-
-
0026137432
-
MPEG: A video compression standard for multi-media applications
-
April
-
GALL, D.L.: 'MPEG: a video compression standard for multi-media applications', Commun. ACM, April 1991, 3-4, pp. 46-58
-
(1991)
Commun. ACM
, vol.3-4
, pp. 46-58
-
-
Gall, D.L.1
-
4
-
-
0029292227
-
A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications
-
MADISETTI, A., and WILLSON, A.N.: 'A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications', IEEE Trans. Circuits Syst. Video Technol, 1995, 5, pp. 158-165
-
(1995)
IEEE Trans. Circuits Syst. Video Technol
, vol.5
, pp. 158-165
-
-
Madisetti, A.1
Willson, A.N.2
-
5
-
-
0026854652
-
A 100-MHz 2-D discrete cosine transform core processor
-
URAMOTO, S., INOUE, Y., TAKABATAKE, A., TAKEDA, J., YAMASHITA, Y., TERANE, H., and YOSHIMOTO, M.: 'A 100-MHz 2-D discrete cosine transform core processor', IEEE J. Solid-State Circuits, 1992, 27, pp. 492-499
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 492-499
-
-
Uramoto, S.1
Inoue, Y.2
Takabatake, A.3
Takeda, J.4
Yamashita, Y.5
Terane, H.6
Yoshimoto, M.7
-
6
-
-
0028733304
-
2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme
-
2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme', IEEE J. Solid-State Circuits. 1994, 29, pp. 1482-1490
-
(1994)
IEEE J. Solid-State Circuits.
, vol.29
, pp. 1482-1490
-
-
Matsui, M.1
Uetani, Y.2
Kim, L.3
Nagamatsu, T.4
Watanabe, Y.5
Chiba, A.6
Matsuda, K.7
Sakuri, T.8
-
7
-
-
0028481156
-
A 0.8μ 100 MHz 2-D DCT core processor
-
JANG, Y., KAO, J., YANG, J., and HUANG, P.: 'A 0.8μ 100 MHz 2-D DCT core processor', IEEE Trans. Consum. Electron., 1994, 40, pp. 703-709
-
(1994)
IEEE Trans. Consum. Electron.
, vol.40
, pp. 703-709
-
-
Jang, Y.1
Kao, J.2
Yang, J.3
Huang, P.4
-
8
-
-
0017538003
-
A fast computation algorithm for the discrete cosine transform
-
CHEN, W., SMITH, C.H., and FRALICK, S.: 'A fast computation algorithm for the discrete cosine transform', IEEE Trans. Commun., 1977, 25, pp. 1004-1009
-
(1977)
IEEE Trans. Commun.
, vol.25
, pp. 1004-1009
-
-
Chen, W.1
Smith, C.H.2
Fralick, S.3
-
10
-
-
0000276706
-
A fast DCT-SQ scheme for images
-
ARAI, Y., AGUI, T., and NAKAJIMA, M.: 'A fast DCT-SQ scheme for images', Trans. IEICE, 1988, E71, pp. 1095-1097
-
(1988)
Trans. IEICE
, vol.E71
, pp. 1095-1097
-
-
Arai, Y.1
Agui, T.2
Nakajima, M.3
-
11
-
-
0029291183
-
New systolic array implementation of the 2-D discrete cosine transform and its inverse
-
CHANG, Y.T., and WANG, C.L.: 'New systolic array implementation of the 2-D discrete cosine transform and its inverse', IEEE Trans. Circuits Syst. Video Technol, 1995, 5, pp. 150-157
-
(1995)
IEEE Trans. Circuits Syst. Video Technol
, vol.5
, pp. 150-157
-
-
Chang, Y.T.1
Wang, C.L.2
-
12
-
-
0027556384
-
Unified parallel lattice structures for time-recursive discrete cosine/sine/hartley transforms
-
RAY-LIU, K., and CHIU, C.T.: 'Unified parallel lattice structures for time-recursive discrete cosine/sine/hartley transforms', IEEE Trans. Signal Process., 1993, 41, pp. 1357-1377
-
(1993)
IEEE Trans. Signal Process.
, vol.41
, pp. 1357-1377
-
-
Ray-Liu, K.1
Chiu, C.T.2
-
13
-
-
0026837632
-
Real-time parallel and fully pipelined two-dimensional DCT lattice structures with application to HDTV systems
-
CHIU, C.T., and RAY-LIU, K.: 'Real-time parallel and fully pipelined two-dimensional DCT lattice structures with application to HDTV systems', IEEE Trans. Circuits Syst. Video Technol., 1992, 2, pp. 25-37
-
(1992)
IEEE Trans. Circuits Syst. Video Technol.
, vol.2
, pp. 25-37
-
-
Chiu, C.T.1
Ray-Liu, K.2
-
14
-
-
79951727925
-
Real-time recursive two-dimensional DCT for HDTV systems
-
March
-
CHIU, C.T., and RAY-LIU, K.: 'Real-time recursive two-dimensional DCT for HDTV systems.' ICASSP-92: IEEE international conference on Acoustics, speech and signal processing, March 1992, Vol. 3, pp. 205-208
-
(1992)
ICASSP-92: IEEE International Conference on Acoustics, Speech and Signal Processing
, vol.3
, pp. 205-208
-
-
Chiu, C.T.1
Ray-Liu, K.2
-
15
-
-
0030083342
-
VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications
-
SRINIVASAN, V., and RAY-LIU, K.: 'VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications', IEEE Trans. Circuits Syst. Video Technol., 1996, 6, pp. 87-96
-
(1996)
IEEE Trans. Circuits Syst. Video Technol.
, vol.6
, pp. 87-96
-
-
Srinivasan, V.1
Ray-Liu, K.2
-
16
-
-
84999115011
-
Full custom VLSI implementation of high-speed 2-D DCT/IDCT chip
-
November
-
SRINIVASAN, V., and RAY-LIU, K.: 'Full custom VLSI implementation of high-speed 2-D DCT/IDCT chip.' IEEE Proceedings ICIP-94, November 1994, Vol. 3, pp. 606-610
-
(1994)
IEEE Proceedings ICIP-94
, vol.3
, pp. 606-610
-
-
Srinivasan, V.1
Ray-Liu, K.2
-
17
-
-
0029359214
-
Computation of discrete cosine transform using Clenshaw's recurrence formula
-
ABURDENE, M.F., ZHENG, J., and KOZICK, R.J.: 'Computation of discrete cosine transform using Clenshaw's recurrence formula', IEEE Signal Process. Lett., 1995, 2, pp. 155-156
-
(1995)
IEEE Signal Process. Lett.
, vol.2
, pp. 155-156
-
-
Aburdene, M.F.1
Zheng, J.2
Kozick, R.J.3
-
18
-
-
0004161838
-
-
Cambridge University Press, UK., 2nd edn.
-
PRESS, W., TEUKOLSKY, S., VETTERLING, W., and FLANNERY, B.: 'Numerical recipes in C: The art of scientific computing'. (Cambridge University Press, UK., 1992, 2nd edn.)
-
(1992)
Numerical Recipes in C: the Art of Scientific Computing.
-
-
Press, W.1
Teukolsky, S.2
Vetterling, W.3
Flannery, B.4
-
19
-
-
0029388830
-
VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor
-
HSIA, S.C., LIU, B.D., YANG, J.F., and BAI, B.L.: 'VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor', IEEE Trans. Circuits Syst. Video Technol. 1995, 5, pp. 396-406
-
(1995)
IEEE Trans. Circuits Syst. Video Technol.
, vol.5
, pp. 396-406
-
-
Hsia, S.C.1
Liu, B.D.2
Yang, J.F.3
Bai, B.L.4
-
20
-
-
0024885515
-
Practical fast 1-D DCT alcorithms with II multiplications
-
LOEFFLER, C., LIGTENBERG, A., and MOSCHYTZ, G.S.: 'Practical fast 1-D DCT alcorithms with II multiplications'. Proceedings of ICASSP, 1989, pp. 988-991
-
(1989)
Proceedings of ICASSP
, pp. 988-991
-
-
Loeffler, C.1
Ligtenberg, A.2
Moschytz, G.S.3
-
21
-
-
0028407773
-
Novel VLSI implementation of (8 × 8) point 2-D DCT
-
MCGOVERN, F.A., WOODS, R.F., and VAN, M.: 'Novel VLSI implementation of (8 × 8) point 2-D DCT', Electron. Lett., 1994, 30, pp. 624-626
-
(1994)
Electron. Lett.
, vol.30
, pp. 624-626
-
-
Mcgovern, F.A.1
Woods, R.F.2
Van, M.3
-
22
-
-
0026925543
-
Fast algorithms for the discrete cosine transform
-
FEIG, E., and WINOGRAD, S.: 'Fast algorithms for the discrete cosine transform', IEEE Trans. Signal Process., 1992, 40, pp. 2174-2193
-
(1992)
IEEE Trans. Signal Process.
, vol.40
, pp. 2174-2193
-
-
Feig, E.1
Winograd, S.2
-
23
-
-
0028996577
-
2-D DCT using on-line arithmetic
-
BRUGUERA, J., and LANG, T.: '2-D DCT using on-line arithmetic.' IEEE international conference on Acoustics, speech and signal processing, 1995, pp. 3275-3278
-
(1995)
IEEE International Conference on Acoustics, Speech and Signal Processing
, pp. 3275-3278
-
-
Bruguera, J.1
Lang, T.2
-
24
-
-
0029246894
-
JAGUAR: A fully pipelined VLSI architecture for JPEG imace compression standard
-
KOVAC, M., and RANGANATHAN, N.: 'JAGUAR: a fully pipelined VLSI architecture for JPEG imace compression standard', Proc. IEEE, 1995, 83, pp. 247-257
-
(1995)
Proc. IEEE
, vol.83
, pp. 247-257
-
-
Kovac, M.1
Ranganathan, N.2
-
25
-
-
0029308478
-
A low ROM distributed arithmetic implementation of the forward/inverse DCT/DST using rotations
-
KARATHANASIS, H.C.: 'A low ROM distributed arithmetic implementation of the forward/inverse DCT/DST using rotations', IEEE Trans. Consum. Electron., 1995, 41, pp. 263-272
-
(1995)
IEEE Trans. Consum. Electron.
, vol.41
, pp. 263-272
-
-
Karathanasis, H.C.1
-
26
-
-
0023330761
-
CMOS differential pass-transistor locic desien
-
PASTERNAK, J., and SHUBAT, A.: 'CMOS differential pass-transistor locic desien', IEEE J. Solid-State Circuits, 1987, SSC-22, pp. 216-222
-
(1987)
IEEE J. Solid-State Circuits
, vol.SSC-22
, pp. 216-222
-
-
Pasternak, J.1
Shubat, A.2
-
27
-
-
0029388046
-
VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding
-
MASAKI, T., MORIMOTO, Y., ONOYE, T., and SHIRAKAWA, I.: 'VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding', IEEE Trans. Circuits Syst. Video Technol., 1995, 5, pp. 387-395
-
(1995)
IEEE Trans. Circuits Syst. Video Technol.
, vol.5
, pp. 387-395
-
-
Masaki, T.1
Morimoto, Y.2
Onoye, T.3
Shirakawa, I.4
-
28
-
-
33746143351
-
A novel architecture for VLSI implementation of the 2-D DCT/IDCT
-
CUCCHI, S., and FRATTI, M.: 'A novel architecture for VLSI implementation of the 2-D DCT/IDCT, IEEE, 1992, V, pp. 693-696
-
(1992)
IEEE
, vol.V
, pp. 693-696
-
-
Cucchi, S.1
Fratti, M.2
-
29
-
-
33746105467
-
A data-driven IDCT architecture for low power video applications
-
September
-
XANTHOPOULOS, T., CHANDRAKASAN, A.P., SODINI, C.G., and DALLY, W.J.: 'A data-driven IDCT architecture for low power video applications'. ESSCIRC'96, September 1996
-
(1996)
ESSCIRC'96
-
-
Xanthopoulos, T.1
Chandrakasan, A.P.2
Sodini, C.G.3
Dally, W.J.4
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