Polishing surfaces for integrated circuits

CHEMTECH

Volumn 28, Issue 2, 1998, Pages 38-46

  Mueller, Brian L ^a,b   Steckenrider, J Scott ^a  

^a CABOT CORPORATION   (United States)

^b Microlectron Materials Division   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPOSITION; ELECTRIC PROPERTIES; ELECTROCHEMISTRY; INTEGRATED CIRCUIT MANUFACTURE; MORPHOLOGY; OXIDES; PARTICLE SIZE ANALYSIS; SILICON WAFERS; SURFACES; TECHNOLOGY; TUNGSTEN;

CHEMICAL MECHANICAL PLANARIZATION; INTERLAYER DIELECTRIC; PARTICLE SIZE;

POLISHING;

EID: 0031997285     PISSN: 00092703     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

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2. Kaufman, F.; Hetherington D. Planarization Processes for ULSI Fabrication to the Year 2001 Tutorial; SEMI Technical Programs, SEMICON West 96, San Francisco, 15 July 1996.
3. Wallraff, G. M.; Allen, R. D.; Hinsberg, W. D.; Simpson, L. L.; Kunz, R. R. CHEMTECH 1993, 23(4), 22.
4. Steigerwald, J. M.; Murarka, S. P.; Gutmann, R. J. Chemical Mechanical Planarization of Microelectronics Materials; Wiley & Sons: New York, 1997; Chapter 5.
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8. Steigerwald, J. M.; Murarka, S. P.; Gutmann, R. J. Chemical Mechanical Planarization of Microelectronics Materials; Wiley & Sons: New York, 1997; Chapter 6.
9. Streinz, C.; Ligocki, D.; Myers, T.; Brusic, V. In An Electrochemical Approach to Slurry Characterization and Development for W CMP, Proceedings of the First International Symposium on Chemical Mechanical Planarization (CMP) in IC Device Manufacturing; Electrochemical Society: Pennington, NJ, 1996; p. 115.