Flash memory reliability

Microelectronics Reliability

Volumn 38, Issue 2, 1998, Pages 185-188

  Cappelletti, P ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; RELIABILITY;

FLASH MEMORY;

NONVOLATILE STORAGE;

EID: 0031994416     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(97)00048-6     Document Type: Article

References (10)

1. Cappelletti, P., Panchieri, A. and Ravazzi, L., Mastering key factors which affect Flash memory reliability. In Proc. ESREF'93, Bordeaux, France, 1993.
2. Cappelletti, P. and Ghidini, G., Evaluation methods of thin oxide for Flash memories. In Proc. 7th Workshop on Dielectrics in Microelectronics, Crete, Greece, 1995.
3. Cappelletti, P., Ghezzi, P., Pio, F. and Riva, C., Accelerated current test for fast tunnel oxide evaluation. Proc. ICMTS'91, 1991, 4, 81.
4. Cappelletti, P., Bez, R., Cantarelli, D. and Ravazzi, L., CAST: an electrical stress test to monitor single bit failures in Flash-EEPROM structures. In Proc. 12th Workshop on Non Volatile Semiconductor Memory, Monterey, CA, 1994.
5. Cappelletti, P., Bez, R., Cantarelli, D. and Fratin, L., Failure mechanisms of Flash cell in program/erase cycling. In Proc. IEDM'94, Digest of Technical Papers, 1994, p. 291.
6. Olivo, P., Ricco'. B. and Sangiorgi, E., High field induced voltage dependent oxide charge. Appl. Phys. Lett., 1986, 48, 1135.
7. Yamada, S., Hiura, Y. and Yamane, T. et al., Degradation mechanism of Flash EEPROM programming after program/erase cycles. IEDM Tech. Dig., 1993, 2.5.1., 23.
8. Ong, T. C., Fazio, A., Mielke, N., Pan, S., Righos, N., Atwood, G. and Lai, S., Erratic erase in ETOX™ Flash memory array. VLSI Symp. Tech., 1993. 7A(2), 83.
9. Dunn, C., Kay, C., Lewis, T., Strauss, T., Schreck, J., Hefley, P., Middendorf, M. and San, T., Flash EPROM disturb mechanisms. IEEE/IRPS Proc., 1994, p. 299.
10. Calligaro, C., Manstretta, A., Modelli, A. and Torelli, G., Technological and design constraints for multilevel Flash memories. In Proc. ICECS'96, Rodos, Greece, 1996.