Topography simulation for interconnect deposition

Solid State Technology

Volumn 41, Issue 2, 1998, Pages 77-82

  Rey, Juan C ^a,c,d   Li, Junling ^a,d   Boksha, Victor ^a,d   Adalsteinsson, D ^b   Sethian, J A ^b  

^a Technology Modeling Associates Inc   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c CADENCE DESIGN SYSTEMS   (United States)

^d Division of Avant Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; PROCESS CONTROL; RELIABILITY;

TOPOGRAPHY SIMULATION;

ULSI CIRCUITS;

EID: 0031988278     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (10)

1. J. McVittie et al., SPEEDIE: A Profile Simulator for Etching and Deposition; SPIE, Vol 1392, "Advanced Techniques for IC Processing," pp. 126-137, 1990.
2. T. S. Cale, V. Mahadev, "Feature Scale Transport and Reaction During Low Pressure Deposition Processes," Thin Films; V. 22; Eds. Rossnagel S. and Ulman A.; Academic Press; p. 175, 1996.
3. TERRAIN, Topography Simulation or IC Technology; Reference Manual, Technology Modeling Associates; Sunnyvale, CA, USA.
4. J.A. Sethian, D. Adalsteinsson, "An Overview of Level Set Methods for Etching, Deposition, and Lithography Development," IEEE Transactions on Semiconductor Devices, 10-1, pp.167-184, 1997.
5. S. Osher, J.A. Sethian, "Fronts Propagating with Curvature-Dependent Speed: Algorithms based on Hamilton-Jacobi Formulations," J. Comp. Phys., 79, pp. 12-49, 1988.
6. D. Adalsteinsson, J.A. Sethian, "A Fast Level Set Method for Propagating Interfaces," J. Comp. Physics, 118, pp. 269-277, 1995.
7. J.A. Sethian, "A Fast Marching Level Set Method for Monotonically Advancing Fronts," Proceedings of the National Academy of Sciences, 93, 4, 1996.
8. J.A. Sethian, "Level Set Methods; Evolving Interfaces in Geometry, Fluid Mechanics, Computer Vision and Material Sciences," Cambridge University Press, 1996.
9. W. Wakamiya, et al., "Novel Stacked-capacitor Cell for 64Mb DRAM," ICCAD, 8-5, p. 69.
10. J.G. Bornstein, et al., "3D Topography Simulation of PECVD Dielectrics over Interconnect Geometries," Proc. 3rd Int. Dielectrics for ULSI Multilevel Conference (DUMIC): pp. 411-418, 1997.