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Volumn 32, Issue 6, 1989, Pages 720-738

Micropipelines

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; LOGIC CIRCUITS;

EID: 0024683698     PISSN: 00010782     EISSN: 15577317     Source Type: Journal    
DOI: 10.1145/63526.63532     Document Type: Article
Times cited : (849)

References (19)
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    • (Apr
    • Chaney, T.J., and Molnar, C.E. Anomalous behavior of synchronizer and arbiter circuits. IEEE Trans. Comput. C-22, 4 (Apr. 1973), 421-422.
    • (1973) IEEE Trans. Comput. , vol.C-22 , Issue.4 , pp. 421-422
    • Chaney, T.J.1    Molnar, C.E.2
  • 3
    • 33646910281 scopus 로고
    • Macromodular computer systems
    • R. Stacy and B. Waxman, Eds., Academic Press, New York
    • Clark, W.A., and Molnar, C.E. Macromodular computer systems. Computers in Biomedical Research, Vol. 4, R. Stacy and B. Waxman, Eds., Academic Press, New York, 1974, 45-85.
    • (1974) Computers in Biomedical Research , vol.4 , pp. 45-85
    • Clark, W.A.1    Molnar, C.E.2
  • 4
    • 0023346637 scopus 로고
    • Deadlock-free message routing in multiprocessor interconnection networks IEEE Trans. Comput. 36, 5 (May
    • Dally, W.J., Seitz, C.L. Deadlock-free message routing in multiprocessor interconnection networks IEEE Trans. Comput. 36, 5 (May 1987), 547-553.
    • (1987) , pp. 547-553
    • Dally, W.J.1    Seitz, C.L.2
  • 5
    • 84976839011 scopus 로고
    • Specification and automatic verification of self-timed queues. Computer Systems Laboratory Report, Stanford University
    • Dill, D.L., Nowick, S.M., and Sproull, R.F. Specification and automatic verification of self-timed queues. Computer Systems Laboratory Report, Stanford University, 1988.
    • (1988)
    • Dill, D.L.1    Nowick, S.M.2    Sproull, R.F.3
  • 6
    • 84976820314 scopus 로고
    • Translating programs into delay-insensitive circuits. Ph.D. dissertation, Eindhoven University of Technology
    • Ebergen, J.C. Translating programs into delay-insensitive circuits. Ph.D. dissertation, Eindhoven University of Technology, 1987.
    • (1987)
    • Ebergen, J.C.1
  • 7
    • 84976787880 scopus 로고
    • the skeleton of computer structures. In Computer Engineering, C.G. Bell, J.C. Mudge, and J.E. McNamara, Eds., Digital Press
    • Levy, J.V. Buses, the skeleton of computer structures. In Computer Engineering, C.G. Bell, J.C. Mudge, and J.E. McNamara, Eds., Digital Press, 1978.
    • (1978)
    • Levy, J.V.B.1
  • 8
    • 77957898656 scopus 로고
    • Sequential Circuits
    • Chapter 10, In Switching Theory, Vol 2, Wiley, NY
    • Miller, R.E. “Sequential Circuits”, Chapter 10, In Switching Theory, Vol 2, Wiley, NY, 1965.
    • (1965)
    • Miller, R.E.1
  • 11
    • 85034949049 scopus 로고
    • Trace theory and systolic computations
    • J.W. deBakker, A.J. Nijman, and P.C. Treleaven, Eds, Springer-Verlag
    • Rem, M. Trace theory and systolic computations. In Proc. PARLE (Parallel Architectures and Languages Europe), Vol 1, J.W. deBakker, A.J. Nijman, and P.C. Treleaven, Eds, Springer-Verlag, 1987, pp. 14-34.
    • (1987) Proc. PARLE (Parallel Architectures and Languages Europe) , vol.1 , pp. 14-34
    • Rem, M.1
  • 12
    • 0024070224 scopus 로고
    • Q-modules: Locally clocked delay-insensitive modules
    • (Sept
    • Rosenberger, F.U., Molnar, C.E., Chaney, T.J., et al. Q-modules: Locally clocked delay-insensitive modules. IEEE Trans. Comput. 37, 9 (Sept. 1988), 1005-1018.
    • (1988) IEEE Trans. Comput. , vol.37 , Issue.9 , pp. 1005-1018
    • Rosenberger, F.U.1    Molnar, C.E.2    Chaney, T.J.3
  • 13
    • 0001951703 scopus 로고
    • System Timing
    • C.A. Mead and L.A. Conway, Eds., Addison-Wesley
    • Seitz, C.L. System Timing. In Introduction to VLSI Systems, C.A. Mead and L.A. Conway, Eds., Addison-Wesley, 1980.
    • (1980) Introduction to VLSI Systems
    • Seitz, C.L.1
  • 14
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    • A clipping divider
    • Thompson Books, Washington, D.C., 765
    • Sproull, R.F., and Sutherland, I.E. A clipping divider. FJCC 1968, Thompson Books, Washington, D.C., 765.
    • (1968) FJCC
    • Sproull, R.F.1    Sutherland, I.E.2
  • 15
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    • Reentrant polygon clipping
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    • Sutherland, I.E., and Hodgman, G.W. Reentrant polygon clipping. Commun. ACM 17, 1 (Jan. 1974), 32-42.
    • (1974) Commun. ACM , vol.17 , Issue.i , pp. 32-42
    • Sutherland, I.E.1    Hodgman, G.W.2
  • 16
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    • Asynchronous queue system, U.S. Patent 4, 679, 213, July 7
    • Sutherland, I.E. Asynchronous queue system, U.S. Patent 4, 679, 213, July 7, 1987.
    • (1987)
    • Sutherland, I.E.1
  • 17
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    • Asynchronous first-in-first-out register structure. US Patent Pending
    • Sutherland, I.E., Asynchronous first-in-first-out register structure. US Patent Pending.
    • Sutherland, I.E.1
  • 18
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  • 19
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.