A compact model for the grounded-gate nMOS transistor behaviour under CDM ESD stress

Journal of Electrostatics

Volumn 42, Issue 4, 1998, Pages 351-381

  Russ, Christian ^a   Verhaege, Koen ^a,b   Bock, Karlheinz ^a   Roussel, Philippe J ^a   Groeseneken, Guido ^a   Maes, Herman E ^a  

^a IMEC   (Belgium)

^b SARNOFF CORPORATION   (United States)

Author keywords

CDM; Circuit simulation; Compact model; ESD protection

Indexed keywords

BIPOLAR TRANSISTORS; COMPUTER SIMULATION; ELECTRIC DISCHARGES; ELECTRIC FIELD EFFECTS; ELECTROSTATICS; MATHEMATICAL MODELS; STRESS ANALYSIS;

ELECTRICAL OVERSTRESSES;

MOS DEVICES;

EID: 0031693937     PISSN: 03043886     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0304-3886(97)00162-9     Document Type: Article

References (19)

1. L. Avery, Charged device model testing - trying to duplicate reality, in: Proc. EOS/ESD Symp., 1987, pp. 88-92.
2. K. Verhaege, G. Groeseneken, H.E. Maes, P. Egger, H. Gieser, Influence of tester, test method and device type on CDM ESD testing, in: Proc. EOS/ESD Symp., 1994, pp. 49-62.
3. H. Gieser, P. Egger, Influence of tester parasitics on charged device model failure thresholds, in: Proc. EOS/ESD Symp., 1994, pp. 69-84.
4. T. Maloney, Designing MOS inputs and outputs to avoid oxide failure in the charged device model, in: Proc. EOS/ESD Symp., 1988, pp. 220-227.
5. N. Macne, J. Vandenbroeck, L. van den Bempt, A study of CMOS integrated circuits charged device model ESD failure modes, in: Proc. 4th ESREF Symp., Arcachon, France, 1993, pp. 407-412.
6. C. Duvvury, How fast does a protection device turn on?, Threshold - ESD Association Newsletter, ESD Association, 7902 Turin Rd. Ste 4, Rome, NY 13440-2069, e-mail 73163.1426@Compu-Serve.com, December 1995, pp. 1, 9.
7. C.H. Diaz, S.-M. Kang, C. Duvvury, Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices, IEEE Trans. CAD ICs Circuits 13 (1994) 482-493.
8. C. Russ, P. Egger, H. Gieser, S. Irl, Compact electro-thermal simulation of ESD-protection elements, Quality and Reliability Engineering International 10 (1994) 335-340.
9. J.R.M. Luchies, C.G.C.M. de Kort, J.F. Verweij, Fast turn-on of an nMOS ESD protection transistor; measurements and simulations, in: Proc. EOS/ESD Symp., 1994, pp. 266-272.
10. J.R.M. Luchies, K. Verhaege, F. Kuper, A. Mouthaan, H. de Graaff, Fast transient ESD simulation of the nMOS protection transistor, in: Proc. 25th ESSDERC Conf., The Hague, The Netherlands, 1995, pp. 307-310.
11. F. Tailliet, J.-P. Chante, Characterisation of an n-p-n structure under ESD stress and proposed electrical model, IEEE Trans. Electron Dev. 37 (April 1990) 1111-1120.
12. A. Amerasekera, S. Ramaswamy, M.-C. Chang, C. Duvvury, Modelling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations, in: Proc. IRPS Symp., 1996, pp. 318-326.
13. R. W. Dutton, Bipolar transistor modelling of avalanche generation for computer circuit simulation, IEEE Trans. Electron Dev. 22 (1975) 334-338.
14. F.-C. Hsu, P.-K. Ko, S. Tam, C. Hu, R.S. Muller, An analytical breakdown for short-channel MOSFETs, IEEE Trans. Electron Dev. 29 (1982) 1735-1740.
15. D. Scott, G. Giles, J. Hall, A lumped element model for the simulation of ESD failures in silicided devices, in: Proc. EOS/ESD Symp., 1986, pp. 41-47.
16. M. Pinto-Guedes, P.C. Chan, A circuit simulation model for bipolar-induced breakdown in MOSFETs, IEEE Trans. Computer-Aided Design 7 (1988) 289-294.
17. T. Skotnicki, G. Merckel, C. Denat, Triggering and sustaining of snapback in MOSFETs, Solid State Electronics 35 (1990) 717-721.
18. B.H. Krabbenborg, H.C de Graaff, A.J. Mouthaan, Analytical calculation of avalanche and thermal snapback points in bipolar transistors, in: Proc. ESSDERC Conf., Edinburgh, UK, 1994, pp. 433-436.
19. B.H. Krabbenborg, Modelling and simulation of electrothermal interaction in bipolar transistors, Ph.D. thesis, Technical University Twente, The Netherlands, 1995.