An Experimental Evaluation of Local Search Heuristics for Graph Partitioning

Computing (Vienna/New York)

Volumn 60, Issue 2, 1998, Pages 121-132

  Ganley, J L ^a   Heath, L S ^b  

^a CADENCE DESIGN SYSTEMS   (United States)

^b State University   (United States)

Author keywords

Genetic algorithms; Graph layout; Graph partitioning; Local search; Simulated annealing; Tabu search

Indexed keywords

COMPUTATIONAL METHODS; GENETIC ALGORITHMS; GRAPH THEORY; PROBLEM SOLVING; SET THEORY; SIMULATED ANNEALING;

GRAPH PARTITIONING; LOCAL SEARCH HEURISTICS; TABU SEARCH;

HEURISTIC METHODS;

EID: 0031679079     PISSN: 0010485X     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF02684361     Document Type: Article

References (34)

1. Bain, L. J., Engelhardt, M.: Introduction to probability and mathematical statistics. Belmont: Duxbury Press 1992.
2. Barnard, S. T., Simon, H. D.: Fast multilevel implementation of recursive bisection for partitioning unstructured problems. Concurrency 6, 101-117 (1994).
3. Berger, M. J., Bokhari, S. H.: A partitioning strategy for nonuniform problems on multiprocessors. IEEE Trans. Comput. 36, 570-580 (1987).
4. Berman, F., Snyder, L.: On mapping parallel algorithms into parallel architectures. J. Parallel Distrib. Comput. 4, 439-458 (1987).
5. Bhatt, Sandeep, N., Thomson Leighton, F.: A framework for solving VLSI graph layout problems. J. Comput. Syst. Sci. 28, 300-343 (1984).
6. Bollobás, B.: Random graphs. Orlando: Academic Press 1985.
7. Bui, T. N., Jones, C.: Finding good approximate vertex and edge partitions is NP-hard. Inform. Proc. Lett. 42, 153-159 (1992).
8. Cohoon, J. P.: Personal communication (1992).
9. Cohoon, J. P., Hedge, S. U., Martin, W. N., Richards, D.: Distributed genetic algorithms for the floorplan design problem. IEEE Trans. Comput. Aided Des. 10, 483-492 (1991).
10. Cohoon, J. P., Paris, W. D.: Genetic placement. IEEE Trans. Comput. Aided Des. 6, 956-964 (1987).
11. David, V., Fraboul, Ch., Rousselot, J. Y., Siron, P.: Partitioning and mapping communication graphs on a modular reconfigurable parallel architecture. In: Parallel Processing: CONPAR 92 - VAPP V, pp. 43-48. Berlin Heidelberg New York Tokyo: Springer 1992.
12. Denning, P. J.: Genetic algorithms. Am. Sci. 80, 12-14 (1992).
13. Even, G., Naor, J., Rao, S., Schieber, B.: Divide-and-conquer approximation algorithms via spreading metrics. In: 36th IEEE Symp. on Foundations of Computer Science, pp. 62-71 (1995).
14. Fiduccia, C. M., Mattheyses, R. M.: A linear-time heuristic for improving network partitions. In: Proceedings of the 19th IEEE Design Automation Conference, pp. 175-181 (1982).
15. Franklin, M. A., Wann, D. F., Thomas, W. J.: Pin limitations and partitioning of VLSI interconnection networks. IEEE Trans. Comput. 31, 1109-1116 (1982).
16. Ganley, J. L., Heath, L. S.:Heuristics for laying out information graphs. Computing 52, 389-405 (1994).
17. Ganley, J. L., Heath, L. S.: Optimal and random partitions of random graphs. Comput. J, 37, 641-643 (1994).
18. Garey, M. R., Johnson, D. S.: Computers and intractability: a guide to the theory of NP-completeness. San Francisco: W. H. Freeman 1979.
19. Glover, F.: Tabu search - part I. ORSA J. Comput. 1, 190-206 (1989).
20. Glover, F.: Tabu search - part II. ORSA J. Comput. 2, 4-32 (1990).
21. Goldberg, D. E.: Genetic algorithms in search, optimization, and machine learning. Reading: Addison-Wesley 1989.
22. Heath, L. S., Rosenberg, A. L., Smith, B. T.: The physical mapping problem for parallel architectures. J. Ass. Comput. Machin. 35, 603-631 (1988).
23. Hendrickson, B., Leland, R.: An improved spectral graph partitioning algorithm for mapping parallel algorithms. SIAM J. Sci. Comput. 16, 452-469 (1995).
24. Johnson, D. S., Aragon, C. R., McGeoch, L. A., Schevon, C.: Optimization by simulated annealing; part I, graph partitioning. Oper. Res. 37, 865-892 (1989).
25. Lavinus, J. W. (aka Ganley, J. L.): Heuristics for laying out information graphs. Master's thesis, Department of Computer Science, Virginia Polytechnic Institute and State University, 1992. Available as Technical Report ST92-01.
26. Moldovan, D. I., Fortes, J. A. B.: Partitioning and mapping algorithms into fixed size systolic arrays. IEEE Trans. Comput. 35, 1-12 (1986).
27. Preas, B. T., Lorenzetti, M. J. (eds.): Physical design automation of VLSI systems. Benjamin/Cumming Publishing Company, Melno Park, California, 1988.
28. Rose, J. S., Klebsch, W., Wolf, J.: Temperature measurement and equilibrium dynamics of simulated annealing placement. IEEE Trans. Comput. Aided Des. 9, 253-259 (1990).
29. Rosenberg, A. L., Heath, L. S.: Graph separators, with applications. New York: Plenum Press 1998.
30. Sarkar, Vivek.: Partitioning and scheduling parallel programs for multiprocessors. Cambridge: MIT Press 1989.
31. Sarkar, Vivek., Hennessy, John. L.: Compile-time partitioning and scheduling of parallel programs. SIGPLAN Notices 21, 17-26 (1986).
32. Shahookar, K., Mazumder, P.: A genetic approach to standard cell placement using metagenetic parameter optimization. IEEE Trans. Comput. Aided Des. 9, 500-511.
33. van Laarhoven, P. J. M., Aarts, E. H. L.: Simulated annealing: theory and applications. Boston: D. Reidel 1987.
34. Varanelli, J. M., Cohoon, J. P.: Two-stage simulated annealing. In: Proceedings of the 4th ACM/SIGDA Physical Design Workshop, pp. 1-10 (1993).