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Volumn , Issue , 1998, Pages 406-413

Low-power driven scheduling and binding

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; HEURISTIC METHODS; SWITCHING;

EID: 0031675044     PISSN: 10661395     EISSN: None     Source Type: None    
DOI: 10.1109/GLSV.1998.665335     Document Type: Conference Paper
Times cited : (5)

References (16)
  • 1
    • 61949152511 scopus 로고
    • A Survey of Optimization Techniques Targeting Low Power VLSI Circuits
    • S. Devadas S. Malik A Survey of Optimization Techniques Targeting Low Power VLSI Circuits Design Automation Conference Design Automation Conference 1995
    • (1995)
    • Devadas, S.1    Malik, S.2
  • 4
    • 85176689462 scopus 로고    scopus 로고
    • Scheduling Techniques to Enable Power Management
    • J. Monteiro S. Devadas P. Ashar A. Mauskar Scheduling Techniques to Enable Power Management Design Automation Conference Design Automation Conference 1996
    • (1996)
    • Monteiro, J.1    Devadas, S.2    Ashar, P.3    Mauskar, A.4
  • 5
    • 85176667963 scopus 로고
    • Variable Voltage Scheduling
    • S. Raje M. Sarrafzadeh Variable Voltage Scheduling International Symposium on Low Power Design International Symposium on Low Power Design 1995
    • (1995)
    • Raje, S.1    Sarrafzadeh, M.2
  • 6
    • 0012184667 scopus 로고    scopus 로고
    • Power Macromodeling for High Level Synthesis Power Estimation
    • S. Gupta F. Najm Power Macromodeling for High Level Synthesis Power Estimation ACM/IEEE Design Automation Conference ACM/IEEE Design Automation Conference 1997
    • (1997)
    • Gupta, S.1    Najm, F.2
  • 7
    • 85176667447 scopus 로고
    • An Iterative Improvement Algorithm for Low Power Data Path Synthesis
    • A. Raghunathan N. Jha An Iterative Improvement Algorithm for Low Power Data Path Synthesis International Conference on Computer Aided Design International Conference on Computer Aided Design 1995
    • (1995)
    • Raghunathan, A.1    Jha, N.2
  • 8
    • 85176686953 scopus 로고
    • Behavioral Synthesis for Low Power
    • A. Raghunathan N. Jha Behavioral Synthesis for Low Power ICCD ICCD 1994
    • (1994)
    • Raghunathan, A.1    Jha, N.2
  • 9
    • 85176687820 scopus 로고
    • Simultaneous Scheduling and Binding for Power Minimization During Microarchitecture Synthesis
    • California
    • A. Dasgupta R. Karri Simultaneous Scheduling and Binding for Power Minimization During Microarchitecture Synthesis International Symposium on Low-Power Design International Symposium on Low-Power Design Dana Point California 1995
    • (1995)
    • Dasgupta, A.1    Karri, R.2
  • 10
    • 0003113577 scopus 로고
    • Black-Box Capacitance Models for Architectural Power Analysis
    • P. Landman J. Rabaey Black-Box Capacitance Models for Architectural Power Analysis International Workshop on Low Power Design International Workshop on Low Power Design 1994
    • (1994)
    • Landman, P.1    Rabaey, J.2
  • 11
    • 0000440896 scopus 로고
    • Architectural Power Analysis: The Dual Bit Type Method
    • P. Landman J. Rabaey Architectural Power Analysis: The Dual Bit Type Method IEEE Trans. on VLSI Systems 3 173 187 1995
    • (1995) IEEE Trans. on VLSI Systems , vol.3 , pp. 173-187
    • Landman, P.1    Rabaey, J.2
  • 12
    • 85176692445 scopus 로고    scopus 로고
    • Exploiting Regularity for Low-Power Design
    • R. Mehra J. Rabaey Exploiting Regularity for Low-Power Design ICC AD ICC AD 1996
    • (1996)
    • Mehra, R.1    Rabaey, J.2
  • 13
    • 0030206111 scopus 로고    scopus 로고
    • Low Power Architectural Synthesis and the Impact of Exploiting Locality
    • R. Mehra L. Guerra J. Rabaey Low Power Architectural Synthesis and the Impact of Exploiting Locality Journal of VLSI Signal Processing 13 239 258 1996
    • (1996) Journal of VLSI Signal Processing , vol.13 , pp. 239-258
    • Mehra, R.1    Guerra, L.2    Rabaey, J.3
  • 14
    • 85176682409 scopus 로고
    • Memory Segmentation to Exploit Sleep Mode Operation
    • A. Farrahi G. Tellez M. Sarrafzadeh Memory Segmentation to Exploit Sleep Mode Operation Design Automation Conference Design Automation Conference 1995
    • (1995)
    • Farrahi, A.1    Tellez, G.2    Sarrafzadeh, M.3
  • 16
    • 85176681196 scopus 로고    scopus 로고
    • Accurate High Level Datapath Power Estimation
    • J. Crenshaw M. Sarrafzadeh Accurate High Level Datapath Power Estimation European Design and Test Conference European Design and Test Conference 1997
    • (1997)
    • Crenshaw, J.1    Sarrafzadeh, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.