Hierarchical functional timing analysis

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 580-585

  Kukimoto, Yuji ^a   Brayton, Robert K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; TIMING CIRCUITS; COMBINATORIAL CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; HIERARCHICAL SYSTEMS; MATHEMATICAL MODELS;

HIERARCHICAL ANALYSIS; HIERARCHICAL APPROACH; HIERARCHICAL TIMING ANALYSIS; LOSS OF ACCURACY; STATE OF THE ART; TIMING ANALYSIS; TIMING CHARACTERIZATION; TOPOLOGICAL ANALYSIS;

TOPOLOGY; TIMING CIRCUITS;

HIERARCHICAL FUNCTIONAL TIMING ANALYSIS; TOPOLOGICAL ANALYSIS;

EID: 0031645147     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277197     Document Type: Conference Paper

References (9)

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