Timing abstraction of intellectual property blocks

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1997, Pages 99-102

  Venkatesh, S V ^a   Palermo, Robert ^a   Mortazavi, Mohammad ^a   Sakallah, Karem A ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER AIDED LOGIC DESIGN; MATHEMATICAL MODELS; SEQUENTIAL CIRCUITS; SYNCHRONIZATION;

BLOCK CHARACTERIZATION; INTELLECTUAL PROPERTY BLOCKS; TIMING ABSTRACTION;

TIMING CIRCUITS;

EID: 0030701050     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)