Reconfiguration for power saving in real-time motion estimation

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 5, Issue , 1998, Pages 3037-3040

  Park, S R ^a   Burleson, W ^a  

^a University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RE-CONFIGURATION; FRAME-BY-FRAME BASIS; HARDWARE CONFIGURATIONS; HARDWARE IMPLEMENTATIONS; LOW POWER IMPLEMENTATION; OFF-CHIP COMMUNICATION; REAL-TIME IMPLEMENTATIONS; VIDEO COMPRESSION ALGORITHMS;

ALGORITHMS; DYNAMIC MODELS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; MOTIVATION; REAL TIME CONTROL; RECONFIGURABLE HARDWARE; SIGNAL PROCESSING;

MOTION ESTIMATION;

EID: 0031642305     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.1998.678166     Document Type: Conference Paper

References (8)

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