Modeling the power rails in leading edge microprocessor packages

Proceedings - Electronic Components and Technology Conference

Volumn Part F133492, Issue , 1998, Pages 598-604

  Michalka, T L ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK COMPONENTS; COMPUTER SIMULATION; ELECTRONICS PACKAGING;

ELECTRICAL MODELING; FLIP CHIP BUMPS; HIGH-PERFORMANCE MICROPROCESSORS; MODEL COMPLEXITY; PHYSICAL STRUCTURES; PRACTICAL GUIDELINES; SPICE MODELING; TWO-DIMENSIONAL ARRAYS;

FLIP CHIP DEVICES; MICROPROCESSOR CHIPS;

GRID ARRAY PACKAGES; POWER RAILS; SOFTWARE PACKAGE SPICE; SUBCIRCUIT MODELS;

EID: 0031640128     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.1998.678756     Document Type: Conference Paper

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