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Volumn 3, Issue , 1998, Pages 1766-1769

Parallel fast multipole capacitance solver

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRICAL ENGINEERING; RADIO; ALGORITHMS; COMPUTATIONAL COMPLEXITY; PROBLEM SOLVING;

EID: 0031637737     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APS.1998.690962     Document Type: Conference Paper
Times cited : (5)

References (6)
  • 2
    • 85056804819 scopus 로고
    • A licrarcliical o(n log n) force calculatiori algoritlini
    • December
    • J. Rariics and I. Ilirt, "A Licrarcliical O(N log N) force calculatiori algoritlini, " Nalarr, vol. 321, IJ. 44G-449, D, ccrmber 1986.
    • (1986) Nalarr , vol.321 , Issue.1 , pp. 44G-449
    • Rariics, J.1    Ilirt, J.2
  • 4
    • 0020115593 scopus 로고
    • Microstrip capacitance for a circular disk throilgh method asymplotic expansions
    • April
    • W. Chew and J. Kong, "Microstrip capacitance for a circular disk throilgh method asymplotic expansions, ' SIAM Journal of Applied Atolheaialirs, vol. 12, pp. 302.316, April 1982.
    • (1982) SIAM Journal of Applied Atolheaialirs , vol.12 , pp. 302-316
    • Chew, W.1    Kong, J.2
  • 5
    • 85053500649 scopus 로고    scopus 로고
    • FastCap: A maltipole-accel-rate-3l-d capacitancr extraction program
    • November 1091
    • K. Nahors and J. While, "FastCap: a maltipole-accel-rate-3l-d capacitancr extraction program." IEEE Trasection on Computer-Aided Design, vol. 10, pp. 1417-1459, November 1091.
    • IEEE Trasection on Computer-Aided Design , vol.10 , pp. 1417-1459
    • Nahors, K.1    While, J.2
  • 6
    • 0030394807 scopus 로고    scopus 로고
    • A parallel multipole accelerate 3d capaciance simulator based on an improved model
    • Dccmihcr
    • Z. Wang, Y. Yuan, and Q. Wu, "A parallel multipole accelerate 3d capaciance simulator based on an improved model, ", IEEE Trasaction of Computer-Aided Disign of Intergrated Circuits and System, vol. 15. Pp 1411-1450, Dccmihcr 1996.
    • (1996) IEEE Trasaction of Computer-Aided Disign of Intergrated Circuits and System , vol.15 , pp. 1411-1450
    • Wang, Z.1    Yuan, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.