A new analytic model of simultaneous switching noise in CMOS systems

Proceedings - Electronic Components and Technology Conference

Volumn Part F133492, Issue , 1998, Pages 615-621

  Cha, Hye Ran ^a   Kwon, Oh Kyong ^a  

^a Hanyang University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODELS; NETWORK COMPONENTS; SPICE; COMPUTER SIMULATION; POWER SUPPLY CIRCUITS; SEMICONDUCTOR DEVICE MODELS; SPURIOUS SIGNAL NOISE; SWITCHING CIRCUITS;

ANALYTIC MODELING; CMOS CIRCUITS; CMOS SYSTEMS; DESIGN GUIDE; GROUND LINES; HSPICE SIMULATIONS; POWER SUPPLY; SIMULTANEOUS SWITCHING NOISE;

CMOS INTEGRATED CIRCUITS;

DRIVER CIRCUITS; SIMULTANEOUS SWITCHING NOISE (SSN); SOFTWARE PACKAGE HSPICE;

EID: 0031628859     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.1998.678759     Document Type: Conference Paper

References (7)

1. A. J. Rainal, "Computing inductive noise of chip packages, " AT&T Bell Labs Tech J., vol. 63, pp. 177-195, Jan. 1984.
2. G. Katopis, "Delta I noise specification for a high performance computer machine, " Proc. IEEE, Sept. 1985, vol. 73, pp. 1405-1415.
3. R. Senthinathan and J. L. Prince, "Simultaneous switching ground noise calculation for packaged CMOS devices, " IEEE JSSC, vol. 26, pp. 1724-1728, Nov. 1991.
4. A. Vaidyanath, B. Thoroddsen, J. L. Prince, "Effect of CMOS driver loading conditions on simultaneous switching noise, " IEEE Trans. CPMT-PART B, vol. 17, pp. 480-485, Nov. 1994.
5. H. Shichman and D. A. Hodges, "Modeling and simulation of insulated gate field effect transistor switching circuits, " IEEE JSSC, vol. SC-3, pp. 285-289, Sept. 1968.
6. T. Sakurai and A. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulations, " IEEE JSSC, vol. 25, pp. 584-594 Apr. 1990
7. S. R. Vemuru, "Accurate simultaneous switching noise estimation including velocity-saturation effect, " IEEE Trans. CPMT-PART B, vol., 19, pp. 344-349, May. 1996.