Using reconfigurable computing techniques to accelerate problems in the CAD domain: A case study with Boolean satisfiability

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 194-199

  Zhong, Peixin ^a   Ashar, Pranav ^a   Malik, Sharad ^a   Martonosi, Margaret ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; COMPUTER AIDED DESIGN; COMPUTER CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; LOGIC GATES; LOGIC SYNTHESIS; MODEL CHECKING; RECONFIGURABLE ARCHITECTURES; BOOLEAN FUNCTIONS; COMPUTER HARDWARE; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS; PARALLEL PROCESSING SYSTEMS; PROBLEM SOLVING;

BOOLEAN OPERATIONS; BOOLEAN SATISFIABILITY; BOOLEAN SATISFIABILITY PROBLEMS; CONFIGURABLE HARDWARE; FINE GRAIN PARALLELISM; QUANTITATIVE STUDY; RECONFIGURABLE COMPUTING; SOFTWARE APPROACH;

COMPUTER AIDED LOGIC DESIGN; COMPUTER AIDED DESIGN;

BOOLEAN SATISFIABILITY PROBLEMS;

EID: 0031624029     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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