Low power signal processing architectures using residue arithmetic

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 5, Issue , 1998, Pages 3017-3020

  Bhardwaj, Manish ^a   Balaram, Arjun ^a  

^a Siemens Components Pie Limited   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

256-POINT FFT; CONTROL COMPLEXITY; OPERATING FREQUENCY; PEAK CURRENTS; POWER CHARACTERISTIC; POWER REDUCTIONS; RECENT TRENDS; RESIDUE ARITHMETIC;

COMMERCE;

SIGNAL PROCESSING;

EID: 0031623969     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.1998.678161     Document Type: Conference Paper

References (12)

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9. J. M, Rabaey and M. Pedram, "Low Power Design Methodologies," Kluwer Academic Publishers, Sept. 1995.
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12. N. S. Szabo and R. I. Tanaka, "Residue Arithmetic and its applications to Computer Technology", McGraw-Hill, 1967.