The impact of device scaling limits

Applied Surface Science

Volumn 117-118, Issue , 1997, Pages 1-10

  Terman, Lewis M ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Device miniaturization; Scaling law

Indexed keywords

COST EFFECTIVENESS; LITHOGRAPHY; PRODUCT DESIGN;

SCALING LAW; SEMICONDUCTOR DEVICE MINIATURIZATION;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0031548649     PISSN: 01694332     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0169-4332(97)80043-8     Document Type: Article

References (27)

1. C.T. Sah, Proc. IEEE, Oktober (1988) 1280-1326.
2. G. Moore, International Electron Devices Meeting Digest, 1975, pp. 11-13.
3. Semiconductor Industries Association National Technology Roadmap for Semiconductors, 1994.
4. R.H. Dennard et al,, IEEE J. Solid-State Circuits, October (1974) 256-268.
5. G. Baccarani et al., IEEE Trans. Electron Devices ED-31 (1984) 452-462.
6. K. Yamabe, K. Taniquichi, IEEE Trans. Electron Devices (1985) 423-428.
7. R.W. Keys, Contemp. Phys. 32 (6) (1991) 403-419.
8. H. Iwai et al, Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications, pp. 262-267
9. A. Deutsch et al., IBM J. Res. Dev. 39 (1995) 547-567.
10. G.A. Sai-Halasz, Proc. IEEE, January (1995) 20-36.
11. M. Levinson et al., IEEE Trans. Electron Devices, December (1992) 1828-2836.
12. K. Kamon et al, Symposium on VLSI Technology Digest, 1992, pp. 108-109.
13. J. Bokev et al, IEEE Circuits Dev. Mag., January (1996) 11-15.
14. B. Hoeneisen, C.A. Mead, Solid State Electron. (1972) 819-829.
15. H.-S. Wong, Y. Taur, International Electron Devices Meetings, 1993, pp. 705-708.
16. T. Mizuno et al, Symposium on VLSI Technology, 1994, pp. 13-14.
17. X. Tang et al, International Symposium on Low Power Electronics and Design, 1996, pp. 233-236.
18. C.M. Melliar-Smith, International Symposium on VLSI Technology, Systems, and Applications, 1995, pp. 8-16.
19. J.D. Meindl, Proc. IEEE, April (1995) 619-635.
20. J.F. Ziegler, IBM J. Res. Dev., January (1996) 41-50.
21. B. Davari et al., Proc. IEEE, April (1995) 595-600.
22. L. Scheffer, International Symposium on VLSI Technology, Systems, and Applications, 1995, pp. 57-62.
23. P. Kogge, Notre Dame University, unpublished work.
24. A.P. Chandrakasan, R.W. Brodersen, Proc. IEEE, April (1995) 498-823.
25. K. Itoh et al., Proc. IEEE, April (1995) 534-543.
26. A. Saulsbury et al., International Symposium on Computer Architecture, 1996, pp. 90-101.
27. T. Shimizu et al., International Solid-State Circuits Conference, 1996, pp. 216-217