Design principles for practical self-routing nonblocking switching networks with O(N · log N) bit-complexity

IEEE Transactions on Computers

Volumn 46, Issue 10, 1997, Pages 1057-1069

  Szymanski, Ted H ^a,b  

^a IEEE   (Canada)

^b MCGILL UNIVERSITY   (Canada)

Author keywords

Circuit switching; Electrical; Multistage; Networks; Nonblocking; Optical; Randomization; Scalable; Self routing

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; CONGESTION CONTROL (COMMUNICATION); DATA COMMUNICATION SYSTEMS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC GATES; PROBABILITY; RANDOM PROCESSES; REDUNDANCY;

SELF ROUTING NONBLOCKING SWITCHING NETWORKS;

INTERCONNECTION NETWORKS;

EID: 0031385399     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.628391     Document Type: Article

References (40)

1. M. Ajtai, J. Komlos, and E. Szemeredi, "An O(NlogN) Sorting Network," Proc. 15th ACM Symp. Theory of Computation, pp. 1-9, 1983.
2. ARPA/ COOP/ AT&T Hybrid-SEED Workshop Notes, George Mason Univ., July 1995.
3. S. Avora, F. Leighton, and B. Maggs, "On Line Algorithms for Path Selection in a Nonblocking Network," Proc. 1990 ACM Symp. Theory of Computing, pp. 149-158, 1990.
4. B.D. Alleyne and I. Scherson, "Expanded Delta Networks for Very Large Parallel Computers," Proc. Int'l Conf. Parallel Processing, pp. 127-131, 1992.
5. A. Bassalygo and M.S. Pinsker, "Complexity of Optimum Nonblocking Switching Network without Reconnections," Problems of Information Transmission, vol. 9, pp. 64-66, 1974.
6. K.E. Batcher, "Sorting Networks and Their Applications," Proc. 1968 Spring Joint Computer Conf., 1968.
7. M.V. Chien and A.Y. Oruc, "Adaptive Binary Sorting Schemes and Associated Interconnection Networks," Proc. Int'l Conf. Parallel Processing, pp. 289-293, 1992.
8. T.J. Cloonan, G.W. Richards, A.L. Lentine, F.B. McCormick, and J.R. Erickson, "Free-Space Photonic Switching Architectures Based on Extended Generalized Shuffles," Applied Optics, vol. 31, no. 35, pp. 7,471-7,492, Dec. 1992.
9. T.J. Cloonan, "Comparative Study of Optical and Electronic Interconnection Technologies for Large Asynchronous Transfer Mode Packet Switching Applications," Optical Eng., vol. 33, no. 5, pp. 1,512-1,523, May 1994.
10. G.A. De Biase, C. Ferrone, and A. Massini, "An O(logN) Depth Asymptotically Nonblocking Self Routing Permutation Network," IEEE Trans. Computers, vol. 44, no. 8, pp. 1,047-1,051, Aug. 1995.
11. B. Douglass, "Rearrangeable Three-Stage Interconnection Networks and Their Routing Properties," IEEE Trans. Computers, vol. 42, no. 5, pp. 559-567, May 1993.
12. H.S. Hinton, T.J. Cloonan, F.B. McCormick, A.L. Lentine, and F.A.P. Tooley, "Free-Space Digital Optical Systems," Proc. IEEE, vol. 82, no. 11, pp. 1,632-1,649, Nov. 1994.
13. W. Hoeffding, "On the Distribution of the Number of Successes in Independent Trials," Annals of Math. Statistics, vol. 27, pp. 713-721, 1956.
14. A. Huang and S. Knauer, "Starlite: A Wideband Digital Switch," Proc. Globecom, Dec. 1988.
15. C.Y. Jan and A.Y. Oruc, "Fast Self-Routing Permutation Switching on an Asymptotically Minimal Cost Network," IEEE Trans. Comm., vol. 42, no. 12, Dec. 1993.
16. R. Kannan, H.F. Jordan, K.Y. Lee, and C. Reed, "A Bit-Controlled Multichannel Time Slot Permutation Network," Proc. Second Int'l Conf. Massively Parallel Processing Using Optical Interconnects, pp. 271-278, 1995.
17. D.M. Koppelman and A.Y. Oruc, "A Self-Routing Permutation Network," J. Parallel and Distributed Computing, vol. 10, pp. 140-151, 1990.
18. A.V. Krishnamoorthy and D.A.B. Miller, "Scaling Optoelectronic-VLSI Circuits into the 21st Century: A Technology Roadmap," IEEE J. Selected Topics in Quantum Electronics, vol. 2, no. 1, pp. 55-76, Apr. 1996.
19. C.P. Kruskal and M. Snir, "The Performance of Multistage Interconnection Networks for Multiprocessors," IEEE Trans. Computers, vol. 32, no. 12, p p. 1,091-1,098, Dec. 1983.
20. FT. Leighton, Parallel Algorithms and Architectures Arrays, Trees and Hypercubes. Morgan-Kaufmann, 1992.
21. A.L. Lentine et al., "700 Mb/ s Operation of Optoelectronic Switching Nodes Comprised of Flip-Chip-Bonded GaAs/ AIGaASMQW Modulators and Detectors on Silicon CMOS Circuitry," Proc. Conf. Lasers and Electrooptics, 1995.
22. 2Years: Part 1," Computer, Apr. 1996, pp. 64-70,
23. T. Lewis, Computer, "Part 2," pp. 78-86, May 1996.
24. D. Mitra and R.A. Cieslak, "Randomized Parallel Communications on an Extension of the Omega Network," J. ACM, vol. 34, pp. 802-824, 1987.
25. Motorola, "OPTOBUS Data Sheet," Logic Integrated Circuits Division, 1995.
26. D. Nassimi and S. Sahni, "Parallel Permutation and Sorting Algorithms and a New Generalized Connection Network," J. ACM, pp. 642-667, 1982
27. J.H. Patel, "Performance of Processor-Memory Interconnections for Multiprocessors," IEEE Trans. Computers, vol. 30, no. 10, pp. 771-780, Oct. 1981.
28. J.L. Hennessey and D.A. Patterson, Computer Architecture, A Quantatative Approach, second edition. San Francisco: Morgan-Kauffman, 1995.
29. Semiconductor Industry Association, "The National Technology Roadmap for Semiconductors," San Jose, Calif.: SIA, 1994.
30. C.E. Shannon, "Memory Requirements in a Telephone Exchange," Bell. Systems Technical J., 1953.
31. S. Sherif, T.H. Szymanski, and H.S. Hinton, "Design and Implementation of a Field Programmable Smart Pixel Array," Proc. LEOS 96 Conf. Smart Pixels, Keystone, Colo., Aug. 1996.
32. B. Supmonchai and T.H. Szymanski, "Fast Self-Routing Concentrators for Optoelectronic Systems," submitted.
33. T.H. Szymanski and V.C. Hamacher, "On the Universality of Multipath Multistage Interconnection Networks," Interconnection Networks, I. Scherson and Youseff, eds., IEEE CS Press, 1994.
34. T.H. Szymanski and C. Fang, "Randomized Routing of Virtual Connections in Essentially Nonblocking log N-Depth Networks," IEEE Trans. Comm., pp. 2,521-2,531, Sept. 1995.
35. T.H. Szymanski and H.S. Hinton, "Reconfigurable Intelligent Optical Backplane for Parallel Computing and Communications," Applied Optics, pp. 1,253-1,268, Mar. 1996.
36. C.D. Thompson, "Generalized Connection Networks for Parallel Processor Intercommunication," IEEE Trans. Computers, vol. 27, no. 12, pp. 1,119-1,125, Dec. 1978.
37. U.S. National Science Foundation, "Research Priorities in Networking and Communications," Report to the NSF Division of Networking and Communications Research and Infrastructure, May 12-14, 1994, Arlington, Va.
38. E. Upfal, S. Felperin, and M Snir, "Randomized Routing with Shorter Paths," IEEE Trans. Parallel and Distributed Systems, vol. 7, no. 4, pp. 356-362, Apr. 1996.
39. L.G. Valiant and G.J Brebner, "Universal Schemes for Parallel Communications," Proc. 13th Ann. ACM Symp. Theory of Computing, pp. 263-277, 1981.
40. M. Yamaguchi, and K-I Yukimatsu, "Recent Free-Space Photonic Switches," IEICE Trans. Comm., vol. E77B, no. 2, Feb. 1994.