The Application of Novel Failure Analysis Techniques and Defect Modeling in Eliminating Short Poly End-Cap Problem in Submicron CMOS Devices

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn 1996-November, Issue , 1996, Pages 165-168

  Hong, Y E ^a   We, M T T ^a  

^a Intel Technology Malaysia Sdn Bhd   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEFECTS; FAILURE (MECHANICAL);

ANALYSIS TECHNIQUES; CMOS DEVICES; DEFECT MODEL; END CAPS; FAILURE MECHANISM; HIGH PACKING DENSITY; HIGH SPEED; PARAMETRIC PROBLEMS; SUBMICRON; SUBMICRON CMOS;

FAILURE ANALYSIS;

EID: 85124093723     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.31399/asm.cp.istfa1996p0165     Document Type: Conference Paper

References (0)