0.8μm CMOS 2.5Gb/s oversampled receiver for serial links

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 200-201

  Yang, Chih Kong Ken ^a   Horowitz, Mark A ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; DATA COMMUNICATION SYSTEMS; ELECTRIC NETWORK ANALYZERS; LOGIC CIRCUITS; MULTIPLEXING; PHASE LOCKED LOOPS; TELECOMMUNICATION LINKS; VARIABLE FREQUENCY OSCILLATORS;

CHIP MICROGRAPH; CIRCUIT DIAGRAM; DEMULTIPLEXING; LOGIC ANALYZER; SERIAL LINKS;

SIGNAL RECEIVERS;

EID: 0030086606     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)