A VHDL-based approach for power estimation of embedded systems

Journal of Systems Architecture

Volumn 44, Issue 1, 1997, Pages 37-61

  Fornaciari, William ^a   Gubian, Paolo ^b   Sciuto, Donatella ^a   Silvano, Cristina ^b  

^a POLITECNICO DI MILANO   (Italy)

^b UNIVERSITY OF BRESCIA   (Italy)

Author keywords

Embedded systems; Low power design; Power estimation; VHDL; VLSI circuits

Indexed keywords

CONSTRAINT THEORY; DATA STORAGE EQUIPMENT; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; VLSI CIRCUITS;

CONTROL LOGIC; DATA PATH; EMBEDDED SYSTEMS; POWER ESTIMATION;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 0031256205     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/S1383-7621(97)80543-7     Document Type: Article

References (28)

1. W.H. Wolf, Hardware-software co-design of embedded systems, Proceedings of the IEEE 82 (7) (1994) 967-989.
2. G. De Micheli, Hardware/Software Co-Design: Application Domains and Design Technologies, Hardware/Software Co-design, NATO ASI Series, Series E: Applied Sciences, vol. 310 Kluwer Academic Publishers, Dordrecht, 1996.
3. P. Landman, High-level power estimation, in: Proceedings of the ISLPED96, International Symposium on Low Power Electronics and Design, Monterey, CA, 1996, pp. 29-35.
4. D. Harel et al., STATEMATE: A working environment for the development of complex reactive systems, IEEE Trans. Software Engrg. 16 (4) (1990) 403-414.
5. V. Nagasamy, N. Berry, C. Dangelo, Specification, planning and synthesis in a VHDL design environment, IEEE Design and Test of Computers, IEEE, NewYork 1992, pp. 58-68.
6. W. Fornaciari, P. Gubian, D. Sciuto, C. Silvano, A conceptual analysis framework for low power design of embedded systems, in: Proceedings of the IEEE International Conference Innovative System in Silicon, Austin, TX, 1996.
7. S. Devadas, S. Malik, A survey of optimization techniques targeting low power VLSI circuits, in: Proceedings of the 32nd IEEE Design Automation Conference, 1995.
8. F.N. Najm, A survey of power estimation techniques in VLSI circuits, IEEE Trans. VLSI Systems 2 (4) (1994) 446-455.
9. A.P. Chandrakasan, R.W. Brodersen, Minimizing power consumption in digital CMOS circuits, Proceeding of the IEEE 83 (4) (1995) 498-523.
10. D. Singh, J. Rabaey, M. Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, T. Mozdzen, Power conscious CAD tools and methodologies: a perspective, Proceedings of the IEEE 83 (4) (1995) 570-594.
11. R. Mehra, J. Rabaey, Behavioural level power estimation and exploration, in: Proceedings of the First International Workshop on Low Power Design, Napa Valley, CA, 1994, pp. 197-202.
12. P.E. Landman, J.M. Rabaey, Power estimation for high-level synthesis, in: Proceedings of the EDAC-EUROASIC'93, European Design Automation Conference, Paris, 1993, pp. 361-366.
13. P.E. Landman, J.M. Rabaey, Architectural power analysis: the dual bit type method, Trans. VLSI Systems 3 (2) (1995), pp. 173-187.
14. P.E. Landman, J.M. Rabaey, Activity-sensitive architec tural power analysis, IEEE Trans. Computer-Aided Design Integrated Circuits and Systems 15 (6) (1996) 571-587.
15. S. Narayan, D.D. Gajski, Area and performance estimation from system-level specifications, Technical Report ICS-92-16, Department of Information and Computer Science, University of California, Irvine, December 20, 1992.
16. T.D. Burd, R.W. Brodersen, Energy efficient CMOS microprocessor design, in: Proceedings of the Hawaii International Conference on System Sciences, Hawaii, 1995.
17. LCB500K, Cell-Based ASIC Design Manual, LSI Logic Corporation, June 1995.
18. C. Svensson, D. Liu, A power estimation tool and prospects of power savings in CMOS VLSI chips, in: Proceedings of the First International Workshop on Low Power Design, Napa Valley, CA, 1994, pp. 171-176.
19. A. Papoulis, Probability, Random Variables and Stochastic Processes, McGraw-Hill, NewYork, 1984.
20. L. Benini, G. De Micheli, State assignment for low power dissipation, IEEE J. Solid State Circuits 30 (3) (1995) 258-268.
21. E. Macii, Sequential synthesis and optimization for low power, Notes of the NATO-ASI Course on Low Power in Deep Submicron Electronics, Kluwer Academic Publishers, Dordrecht, 1996.
22. C.Y. Tsui, M. Pedram, C.A. Cehn, A.M. Despain, Low power state assignment targeting two- and multi-level logic implementations, in: Proceedings of the IC-CAD'1994: IEEE/ACM International Conference on Computer Aided Design, 1994, pp. 82-87.
23. K. Roy, S.C. Prasad, Syclop: synthesis of CMOS logic for low power application, in: Proceedings of the ICCD'92 IEEE International Conference on Computer Design, 1992, pp. 464-467.
24. E. Olson, S.M. Kang, Low-power state assignment for finite state machines, in: Proceedings of the IWLPD'94: ACM/IEEE International Workshop on Low Power Design, Napa Valley, CA, 1994, pp. 63-68.
25. V. Tiwari, S. Malik, A. Wolfe, Power analysis of embedded software: a first step towards software power minimization, IEEE Trans. VLSI Systems 2 (4) (1994) pp. 437-449.
26. A. Balboni, W. Fornaciari, D. Scíuto, TOSCA: A Pragmatic Approach to Co-design Automation of Control Dominated Systems, Hardware/Software Co-design, NATO ASI Series, Series E: Applied Sciences, vol. 310, Kluwer Academic Publishers, Dordrecht, 1996, pp. 265-294.
27. A.V. Aho, R. Sethi, J.D. Ullman (Compilers): Principles, Techniques and Tools, Addison-Wesley, Reading, MA, 1986.
28. F.N. Najm, R. Burch, P. Yang, I.N. Hajj, Probabilistic simulation for reliability analysis of CMOS VLSI circuits, IEEE Trans. Computer-Aided Design, 9 (4) (1990) 439-450 (Errata in July 1990).