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Volumn 144, Issue 5, 1997, Pages 272-276

High-density 16/8/4-bit configurable multiplier

Author keywords

Configurable multiplier; Multiprecision computation; Serial parallel multiplier; Vlsi multiplier

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; TRANSISTORS; VLSI CIRCUITS;

EID: 0031249433     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19971478     Document Type: Article
Times cited : (16)

References (19)
  • 1
    • 0001146101 scopus 로고
    • A signed binary multiplication technique
    • May
    • BOOTH, A.D.: 'A signed binary multiplication technique', Q.J. Mech. Appl. Math., May 1951, 4, Part 2. pp. 236-240
    • (1951) Q.J. Mech. Appl. Math. , vol.4 , Issue.2 PART , pp. 236-240
    • Booth, A.D.1
  • 2
    • 0015077993 scopus 로고
    • A binary multiplication scheme based on squaring
    • CHEN, T.C.: 'A binary multiplication scheme based on squaring', IEEE Trans., 1971, C-20, pp. 678-680
    • (1971) IEEE Trans. , vol.C-20 , pp. 678-680
    • Chen, T.C.1
  • 3
    • 84937739956 scopus 로고
    • A suggestion for a fast multiplier
    • WALLACE, C.S.: 'A suggestion for a fast multiplier', IEEE Trans., 1964, EC-13, pp. 14-17
    • (1964) IEEE Trans. , vol.EC-13 , pp. 14-17
    • Wallace, C.S.1
  • 5
    • 0015724965 scopus 로고
    • A two's complement parallel array multiplication algorithm
    • BAUGH, C.R., and WOOLEY, B.A.: 'A two's complement parallel array multiplication algorithm', IEEE Trans., 1973, C-22, (1-2) pp. 1045-1047
    • (1973) IEEE Trans. , vol.C-22 , Issue.1-2 , pp. 1045-1047
    • Baugh, C.R.1    Wooley, B.A.2
  • 6
    • 0027557033 scopus 로고
    • Finite precision error analysis of neural network hardware implementations
    • HOLT, J.L., and HWANG, J.N.: 'Finite precision error analysis of neural network hardware implementations', IEEE Trans., 1993, C-42, (3) pp. 281-290
    • (1993) IEEE Trans. , vol.C-42 , Issue.3 , pp. 281-290
    • Holt, J.L.1    Hwang, J.N.2
  • 7
    • 0024610868 scopus 로고
    • Design of an efficient VLSI inner-product processor for real time DSP applications
    • Feb.
    • AHMAD, M.O., and POORNALAH, D.V.: 'Design of an efficient VLSI inner-product processor for real time DSP applications', IEEE Trans., Feb. 1989, CAS-36, (2) pp. 324-329
    • (1989) IEEE Trans. , vol.CAS-36 , Issue.2 , pp. 324-329
    • Ahmad, M.O.1    Poornalah, D.V.2
  • 8
    • 0006482139 scopus 로고
    • Computer Science Division, University of California
    • OUSTERHOUT, J.: 'Magic tutorials' (Computer Science Division, University of California, 1990) http://www.research.digital.com:80/wrl/projects/majic
    • (1990) Magic Tutorials
    • Ousterhout, J.1
  • 15
    • 0024648183 scopus 로고
    • SPIM: A Pipelined 64 × 64-bit iterative multiplier
    • Apr.
    • SANTORO, M.R., and HOROWITZ, M.A.: 'SPIM: A Pipelined 64 × 64-bit iterative multiplier', IEEE J. Solid-State Circuits, Apr. 1989, 24, (2), pp. 487-493
    • (1989) IEEE J. Solid-State Circuits , vol.24 , Issue.2 , pp. 487-493
    • Santoro, M.R.1    Horowitz, M.A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.