Self-aligned emitter power HBT and self-aligned gate power HFET for low/unity supply voltage operation in PHS handsets

Solid-State Electronics

Volumn 41, Issue 10, 1997, Pages 1675-1679

  Ota, Yorito ^a   Yamamoto, Shinji ^a   Yokoyama, Takahiro ^a   Masato, Hiroyuki ^a   Nishitsuji, Mitsuru ^a   Yanagihara, Manabu ^a   Inoue, Kaoru ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CURRENT DENSITY; ELECTRIC DISTORTION; ELECTRIC RESISTANCE; HETEROJUNCTION BIPOLAR TRANSISTORS; PERSONAL COMMUNICATION SYSTEMS; SEMICONDUCTING ALUMINUM COMPOUNDS; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTING INDIUM COMPOUNDS; SEMICONDUCTOR DOPING; TELEPHONE SETS;

EMITTER ELECTRODE SELF ALIGNMENT PROCESS;

JUNCTION GATE FIELD EFFECT TRANSISTORS;

EID: 0031245508     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(97)00122-6     Document Type: Article

References (7)

1. Ota, Y., Yanagihara, M., Yokoyama, T., Azuma, C., Maeda, M. and Ishikawa. O., IEEE MTT-S, Technical Digest, 1992, pp. 1517.
2. Yokoyama, T., Kunihisa, T., Fujimoto, H., Takehara, H., Ishida, K., Ikeda H. and Ishikawa, O., IEEE Trans. MTT, 1994, 42, 2623.
3. Inada, M., Ota, Y., Nakagawa, A., Yanagihara, M., Hirose, T. and Eda, K., IEEE Trans Electron Dev., 1987, 34, 2405.
4. Ota, Y., Nakamura, M. and Yanagihara, M., Solid-St. Electron., 1995, 38, 2005.
5. Ota, Y., Nishitsuji, M., Masato, H., Morimoto, S. and Fujimoto, H., Inst. Phys. Conf., 1996, 145, 779.
6. Inoue, K., Nishii, K., Matsuno, T. and Onuma, T., IEDM, Proc., 1987, 422.
7. Nishitsuji, M., Masato, H., Morimoto, S., Inoue, K. and Ota, Y., DRC, Digest, 1996, 130.