Multi-Gb/s operation of flipped chip MVTL circuits

IEEE Transactions on Applied Superconductivity

Volumn 7, Issue 2 PART 3, 1997, Pages 2693-2696

  Dalrymple, Bruce J ^a,b,c   Leung, Michael ^a,b,c   Sandell, Robert D ^a,b,c   John, W ^a,b,c   Trw, Spargo ^a,b,c   Pham, Thi ^a,b,c   Spooner, Alan ^a,b,c  

^a One Space Park   (United States)

^b SGS Thomson   (United States)

^c SMI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; FLIP CHIP DEVICES; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; SOLDERING; SUPERCONDUCTING DEVICES; THRESHOLD LOGIC;

MODIFIED VARIABLE THRESHOLD LOGIC (MVTL) GATES; SUPERCONDUCTIVE DIGITAL CIRCUITS;

LOGIC GATES;

EID: 0031165035     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.621794     Document Type: Article

References (4)

1. N. Fujimaki S. Kotani T. Imamura and S. Hasuo Josephson Modified Variable Threshold Logic Gâtes for Use in Ultra-HighSpeed LSI IEEE Trans. Elect. Dev. Vol. 36 No. 2 pp. 433-446 1989. ;
2. M. Leung J. Spargo B. Dalrymple D. Durand M. Wire and A. Spooner Performance of MVTL Logic at Multi-GHz Frequencies IEEE Trans. Appl. Supercon. Vol. 5 No. 2 pp. 2636-2639 1995.
3. K.E. Yokoyama G. Akerling A. D. Smith and M. Wire Superconducting Die Attach Process unpublished. :
4. Licari James i. Multichip Module Design Fabrication & Testing New York City NY: McGraw-Hill Inc. 1995 p. 48.