Clocking Optimization and Distribution in Digital Systems with Scheduled Skews

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 16, Issue 2-3, 1997, Pages 131-147

  Hsieh, Hong Yean ^a,c,d   Liu, Wentai ^{a,c,d,e,f,g,h}   Franzon, Paul ^a,d,g,h,i   Cavin III, Ralph ^{a,b,d,h,j,k,l,m,n}  

^a North Carolina State University   (United States)

^b Semiconductor Research Center   (United States)

^c NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^d NORTH CAROLINA STATE UNIVERSITY   (United States)

^e NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^f UNIVERSITY OF MICHIGAN   (United States)

^g Dept of Elec and Comp Engineering ^*  (Australia)

^h IEEE

ⁱ LUCENT TECHNOLOGIES   (United States)

^j MISSISSIPPI STATE UNIVERSITY   (United States)

^k AUBURN UNIVERSITY   (United States)

^l Martin Marietta Corporation   (United States)

^m TEXAS A AND M UNIVERSITY   (United States)

ⁿ SEMICONDUCTOR RESEARCH CORPORATION   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; FLIP FLOP CIRCUITS; NATURAL FREQUENCIES; OPTIMIZATION; PROBLEM SOLVING;

CLOCK DISTRIBUTION SCHEME; SCHEDULED SKEWS;

TIMING CIRCUITS;

EID: 0031164194     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (19)

1. H.B. Bakoglu, Circuits, Interconnection, and Packaging for VLSI, Addison-Wesley, 1990.
2. H. Hsieh, W. Liu, C.T. Gray, and R. Cavin, "Concurrent timing optimization of latch-based digital systems," International Conference on Computer Design, pp. 680-685, 1995.
3. C.T. Gray, W. Liu, and R. Cavin III, Wave Pipelining: Theory and CMOS Implementations, Kluwer Academic Publisher, Oct. 1993.
4. J. Neves and E. Friedman, "Design methodology for synthesizing clock distribution networks exploiting non-zero localized clock skew," IEEE Transactions on VLSI Systems, Vol. 4, pp. 286-291, June 1996.
5. J.P. Fishburn, "Clock skew optimization," IEEE Transactions on Computers, Vol. 39, pp. 945-951, July 1990.
6. M. Heshami and B. Wooley, "A 250-MHz skewed-clock pipelined data buffer," IEEE Journal of Solid-State Circuits, Vol. 31, No. 3, pp. 376-383, March 1996.
7. H. Toyoshima, "A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multi-phase PLL," IEEE Journal of Solid-State Circuits, Vol. 30, No. 11, pp. 1189-1202, Nov. 1995.
8. R. Tsay, "An exact zero-skew clock routing algorithm," IEEE Transactions on Computer-Aided Design, Vol. 12, No. 2, pp. 242-249, Feb. 1993.
9. S. Pullela, N. Menezes, and L.T. Pillage, "Reliable non-zero skew clock trees using wire width optimization," 30th Design Automation Conference, pp. 165-170, 1993.
10. R. Watson and R. Iknaian, "Clock buffer chip with multiple target automatic skew compensation," IEEE Journal of Solid-State Circuits, Vol. 30, No. 11, pp. 1267-1276, Nov. 1995.
11. E. Best, Phase Locked Loops: Theory, Design, and Applications, McGraw-Hill, c1984.
12. N. Shenoy et al., "On the temporal equivalence of sequential circuits," 29th Design Automation Conference, pp. 405-409, 1992.
13. M.R. Garey and D.S. Johnson, Computers and Intractability, W.H. Freeman and Company, 1979.
14. T.H. Cormen, C.E. Leiserson, and R.L. Rivest, Introduction to Algorithms, McGraw-Hill, 1990.
15. M. Shoji, "Elimination of process-dependent clock skew in CMOS VLSI," IEEE Transactions on Computers, Vol. C-39, No. 7, pp. 945-951, July 1990.
16. J. Kang, W. Liu, and R. Cavin III, "A monolithic 625Mb/s data recovery circuit in 1.2 μm CMOS," Custom Integrated Circuits Conference, pp. 463-465, March 1994.
17. M.G. Johnson and E.L. Hudson, "A variable delay line PLL for CPU-Coprocessor synchronization," IEEE Journal of Solid-State Circuits, pp. 1218-1223, 1988.
18. C.T. Gray, W. Liu, W. van Noije, T. Hughes, and R. Cavin III, "A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution," IEEE Journal of Solid-State Circuits, Vol. 29, No. 3, pp. 340-349, March 1994.
19. H. Hsieh, Clocking Optimization and Distribution in Digital Systems with Scheduled Skews, Ph.D. Thesis, North Carolina State University, 1996.