Robust superconducting die attach process

IEEE Transactions on Applied Superconductivity

Volumn 7, Issue 2 PART 3, 1997, Pages 2631-2634

  Yokoyama, K E ^a   Akerling, G ^a   Smith, A D ^a   Wire, M ^a  

^a NORTHROP GRUMMAN CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIES; DIGITAL INTEGRATED CIRCUITS; ELECTRIC IMPEDANCE MEASUREMENT; FLIP CHIP DEVICES; INDUCTANCE MEASUREMENT; INTEGRATED CIRCUIT LAYOUT; MULTICHIP MODULES; SOLDERING; THERMAL CYCLING; THERMODYNAMIC STABILITY;

LOW TEMPERATURE SUPERCONDUCTING (LTS) CHIPS; REFLOW SOLDERING;

SUPERCONDUCTING DEVICES;

EID: 0031163483     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.621779     Document Type: Article

References (5)

1. Sandeil R. D. G. Akerling and A. D. Smith MultiChip Packaging For High Speed Superconducting Circuits IEEE Trans on Applied Superconductivity Vol. 5 No. 2 June 1995 pp. 3160-3163.
2. Licari James J. Multichip Module Design. Fabricatibn. & Testing. McGraw-Hill Inc. 1955.
3. Brady M. J. and A. Davidson Flip-chip bonding with solder dipping Rev. Sci. Instrum. 56 (7) July 1985 pp 1459-1460.
4. Wernick J. H. and B. T. Matthias J. Chem. Phys. Vol 34 1961 page 2194.
5. Abelson L. A. S. L. Thomasson J. M. Murducki F Elmadjian G. Akerling R. Kono H. W. Chan Superconductive Integrated Circuit Foundry IEE Trans on Applied Superconductivity Vol. 3 No. March 1993 pp. 2043 - 2049.