Relation between trap creation and breakdown during tunnelling current stressing of sub 3 nm gate oxide

Microelectronic Engineering

Volumn 36, Issue 1-4, 1997, Pages 21-24

  Depas, M ^a   Heyns, M M ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; ELECTRIC BREAKDOWN OF SOLIDS; ELECTRIC CURRENT MEASUREMENT; ELECTRON TUNNELING; GATES (TRANSISTOR); LEAKAGE CURRENTS; MOS DEVICES; SEMICONDUCTOR DEVICE MODELS; SILICA; ULTRATHIN FILMS;

CHARGE TO BREAKDOWN; ELECTRON TRAPS; STRESS INDUCED LEAKAGE CURRENT (SILC); ELECTRON TRAP CREATION; GATE OXIDES; STRESS INDUCED LEAKAGE CURRENTS (SILC); TUNNEL CURRENT INSTABILITY; TUNNELLING CURRENT STRESSING;

DIELECTRIC FILMS; MOS DEVICES;

EID: 0031150213     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(97)00008-7     Document Type: Article

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