A Complementary Pair of Four-Terminal Silicon Synapses

Analog Integrated Circuits and Signal Processing

Volumn 13, Issue 1-2, 1997, Pages 153-166

  Diorio, Chris ^{a,b,c,d,e,f,g}   Hasler, Paul ^a,g,h,i,j   Minch, Bradley A ^a,g,i,j,k,l   Mead, Carver ^{a,g,l,m,n,o,p}  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^b OCCIDENTAL COLLEGE   (United States)

^c NORTHROP GRUMMAN CORPORATION   (United States)

^d American Systems Corporation   (United States)

^e Analytic Sciences Corporation   (United States)

^f Sigma Pi Sigma   (United States)

^g IEEE   (United States)

^h ARIZONA STATE UNIVERSITY   (United States)

ⁱ Tau Beta Pi   (United States)

^j Eta Kappa Nu   (United States)

^k Eta Kappa Nu ^*  (United States)

^l Cornell University ^*

^m NATIONAL ACADEMY OF SCIENCES   (United States)

ⁿ Roy Swed Acad of Eng Sciences

^o AMERICAN PHYSICAL SOCIETY   (United States)

^p The Franklin Institute   (United States)

more..

Author keywords

Floating gate MOSFET; Silicon learning; Synapse transistor

Indexed keywords

ANALOG STORAGE; ELECTRON TUNNELING; LEARNING SYSTEMS; STORAGE ALLOCATION (COMPUTER); TRANSISTORS;

SILICON LEARNING SYSTEMS; SYNAPSE TRANSISTORS;

MOSFET DEVICES;

EID: 0031145731     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008244314595     Document Type: Article

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