Winner-Takes-All Associative Memory: A Hamming Distance Vector Quantizer

Analog Integrated Circuits and Signal Processing

Volumn 13, Issue 1-2, 1997, Pages 211-222

  Pouliquen, Philippe O ^a,b   Andreou, Andreas G ^a,b,c   Strohbehn, Kim ^b,d,e,f  

^a Johns Hopkins University   (United States)

^b JOHNS HOPKINS UNIVERSITY   (United States)

^c Tau Beta Pi   (United States)

^d IOWA STATE UNIVERSITY   (United States)

^e Applied Physics Laboratory   (United States)

^f Space Instrumentation Group ^*  (United Kingdom)

Author keywords

Analog VLSI; Associative memory; Associative processor; Computational memory; Current mode subthreshold circuits; Precision on demand; Smart memory; Vector quantization; Winner Takes All

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; MICROPROCESSOR CHIPS; PATTERN RECOGNITION; RANDOM ACCESS STORAGE; STORAGE ALLOCATION (COMPUTER); VECTOR QUANTIZATION;

NEUROMORPHIC PROCESSOR; WINNER TAKES ALL ASSOCIATIVE MEMORY;

VLSI CIRCUITS;

EID: 0031145282     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008204616413     Document Type: Article

References (25)

1. T. Kohonen, Content-Addressable Memories, 2 edition. Springer Verlag, Berlin, 1987.
2. T. Kohonen, Self-Organization and Associative Memory, 2 edition. Springer Verlag: Berlin, 1988.
3. Mohamad H. Hassoun, editor, Associative Neural Memories: Theory and Implementation. Oxford University Press: New York, New York, 1993.
4. M. R. Emerling M. A. Sivilotti and C. A. Mead, VLSI architectures for implementation of neural networks. In (J. J. Denker, ed.), Neural Networks for Computing. AIP: Snowbird UT, 1986, pages 408-413.
5. K. A. Boahen and A. G. Andreou, "Design of a bidirectional associative memory chip," in Associative Neural Memories: Theory and Implementation (M. Hassoun, ed.), chapter 17. Oxford University Press: New York, NY, 1993.
6. P. O. Pouliquen, A. G. Andreou, K. Strohbehn, and R. E. Jenkins, "An associative memory integrated system for character recognition," in Proc. 36th Midwest Symp. on Circuits and Systems, Detroit, MI, Aug. 1993, pp. 762-765,
7. Y. He, U. Cilingiroglu, and E. Sánchez-Sinencio, "A high density and low-power charge-based hamming network." IEEE Trans. VLSI Systems 1(1), pp. 55-62, March 1993.
8. Y. Horio and S. Nakamura, "Analog memories for VLSI neurocomputing," in Artificial Neural Networks: Paradigms, Applications, and Hardware Implementations (E. Sánchez-Sinencio and C. Lau, eds.), IEEE Press, Piscataway, NJ, 1992, pp. 344-366.
9. G. Cauwenberghs, C. F. Neugebauer, and A. Yariv, "Analysis and verification of an analog VLSI incremental outer-product learning systems." IEEE Trans. Neural Networks 3(3), May 1992.
10. H. Yang, B. J. Sheu, and J.-C. Lee, "A nonvolatile analog neural memory using floating-gate MOS transistors." Analog Integrated Circuits and Signal Processing 2(1), Feb. 1992.
11. K. A. Boahen, P. O. Pouliquen, A. G. Andreou, and R. E. Jenkins, "A heteroassociative memory using current-mode MOS analog VLSI circuits." IEEE Trans. Circuits and Systems CAS-36(5), pp. 747-755, May 1989.
12. K. A. Boahen, A. G. Andreou, and P. O. Pouliquen, "Architectures for associative memories using current-mode analog MOS circuits," in Advanced Research in VLSI: Proc. Dec. Caltech Conference on VLSI (C. L. Seitz, ed.). MIT Press: Cambridge, MA, 1989.
13. Eric Vittoz and J. Fellrath, "CMOS analog integrated circuits based on weak inversion operation." IEEE J. Solid-State Circ. 12, pp. 224-231, 1977.
14. C. A. Mead, Analog VLSI and Neural Systems. Addison-Wesley: Reading, MA, 1989.
15. A. G. Andreou and K. A. Boahen, "Neural information processing II," in Analog VLSI Signal and Information Processing (M. Ismael and T. Fiez, eds.). McGraw-Hill, 1994.
16. K. Seno, K. Knorpp, L.-L. Shu, N. Teshima, H. Kihari, H. Sato, F. Miyaji, M. Takeda, M. Sasaki, Y. Tomo, P. T. Chuang, and K. Kobayashi, "A 9-ns 16-mb CMOS SRAM with offset-compensated current sense amplifier." IEEE J. Solid-State Cicuits 28(11), pp. 1119-1124, November 1993.
17. 2 single bit line memory cell." IEEE J. Solid-State Cicuits 28(11), pp. 1125-1130, November 1993.
18. R. F. Lyon and R. R. Schediwy, "CMOS static memory with a new four-transistor memory cell," in Advanced Research in VLSI (P. Losleben, ed.). MIT Press: Cambridge, MA, 1987, pp. 110-132,
19. G. A. Carpenter and S. Grossberg, "A massively parallel architecture for a self-organizing neural pattern recognition machine." Computer Vision, Graphics, and Image Processing 37, pp. 54-115, 1987.
20. J. Lazzaro, S. Ryckebusch, M. A. Mahowald, and C. Mead, "Winner-take-all networks of o(n) complexity," in Advances in Neural Information Processing Systems 1 (D. Touretzky, ed.). Morgan Kaufmann: San Manteo, CA, 1989, pp. 703-711,
21. B. Gilbert, "Translinear circuits: A proposed classification." Electronics Letters 11(1), pp. 14-16, 136, January 9, 1975.
22. A. G. Andreou and K. A. Boahen, "Translinear circuits in subthreshold mos." J. Analog Integrated Circ. Sig. Proc. 9, pp. 141-166, 1996.
23. A. Pavasović, A. G. Andreou, and C. R. Westgate, "Characterization of subthreshold MOS mismatch in transistors for VLSI systems." Journal of Analog Integrated Circuits and Signal Processing 6, pp. 75-85, July 1994.
24. N. Kumar, P. O. Pouliquen, and A. G. Andreou, "Device mismatch limitations on the performance of an associative memory system," in Proc. 36th Midwest Symp. on Circuits and Systems (IEEE, ed.), 1993, pp. 570-573.
25. H. Miwa, N. Kumar, P. O. Pouliquen, and A. G. Andreou, "Memory enhancement techniques for mixed digital memory analog computational engines," in Proc. IEEE Int. Symp. on Circuits and Systems, volume 5, June 1994, pp. 45-48.